Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters

Abstract

This paper introduces the concept of "Soft Tiles" to capture and exploit physical implementation flexibility within tightly-coupled processing clusters used in modern high-performance architectures. The research explores how varying the size and aspect ratio of these tiles, built using RISC-V cores and shared L1 memory, impacts achievable frequency and energy efficiency. By establishing a hierarchical implementation methodology, the goal is to model clusters as soft tiles to optimize overall die floorplan utilization and maximize silicon efficiency.

Report

Key Highlights

• Soft Tiles Concept: Introduces a novel concept for modeling tightly-coupled parallel processing clusters with inherent physical implementation flexibility.
• Physical Constraints vs. Performance: Focuses on the trade-off where tile size and aspect ratio significantly impact the operating frequency and energy efficiency of high-performance clusters.
• Hierarchical Optimization: Proposes a methodology where clusters are modeled as flexible, or 'soft,' tiles to achieve optimal utilization of the top-level die floorplan.
• Target Architecture: The flexibility analysis is performed on clusters based on RISC-V cores utilizing shared L1 memory, suitable for building scalable accelerators.

Technical Details

• Architectural Target: Multicore, GPU, and Manycore architectures relying on closely interconnected processing elements.
• Core Technology: Uses RISC-V cores as the foundational processing element within the clusters.
• Cluster Structure: Clusters are tightly coupled and incorporate a shared L1 memory structure to facilitate high-bandwidth parallel processing.
• Methodology: The research centers on quantifying the permissible range of flexibility (size and aspect ratio) to determine the performance impact and enable integration into the overarching hierarchical physical design flow.

Implications

• Enhanced RISC-V Customization: Provides essential insights for RISC-V ecosystem developers seeking to build highly optimized Domain-Specific Accelerators (DSAs), allowing the physical design to adapt to complex integration scenarios.
• Silicon Efficiency: By enabling clusters to function as soft, flexible entities, the methodology directly improves overall die utilization, leading to more compact and cost-effective chip designs.
• HPC and Manycore Development: The findings advance the scalability of tightly-coupled clusters, crucial for next-generation High-Performance Computing (HPC) and energy-efficient manycore systems based on RISC-V.
• Advanced Physical Design: This approach bridges the gap between architectural definition and physical implementation, making optimization decisions (frequency, energy) contingent on flexible floorplanning requirements.