SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding

Abstract

SmaRTLy is a novel RTL optimization technique specifically designed to enhance multiplexer tree synthesis by utilizing advanced logic inferencing and structural rebuilding methods. This approach overcomes the limitations of traditional synthesis tools that fail to exploit intrinsic logical relationships among signals. Evaluations on RISC-V and industrial benchmarks show that SmaRTLy achieves superior gate count reduction, yielding an additional 8.95% AIG area reduction on standard sets and 47.2% greater reduction on industrial scale designs compared to Yosys.

Report

Key Highlights

• Core Innovation: Introduces SmaRTLy, a new technique focusing on the optimization and reduction of complex multiplexer trees in Register-Transfer Level (RTL) logic.
• Performance Gain: Achieved an additional 8.95% reduction in AIG (And-Inverter Graph) area across standard academic and RISC-V benchmarks compared to the baseline tool, Yosys.
• Industrial Impact: Demonstrated significant scalability and effectiveness on large industrial designs (millions of gates), removing 47.2% more AIG area than Yosys.
• Methodology Shift: Moves beyond traditional optimization methods, which only monitor control port values, by incorporating deeper analysis through logic inferencing and structural rebuilding.

Technical Details

• Optimization Target: Multiplexer trees, which are recognized as highly common structures in RTL logic that are often sub-optimally handled by conventional synthesis.
• Technical Strategy: SmaRTLy employs two primary strategies: 1) Logic inferencing, used to fully exploit intrinsic logical relationships among signals, and 2) Structural rebuilding, focused on restructuring the remaining logic after redundancy removal.
• Baseline Comparison: The methodology is benchmarked directly against the performance of the well-known open-source synthesis tool, Yosys.
• Evaluation Metrics: The effectiveness of the optimization is measured based on the reduction in AIG area (representing minimized gate count).
• Benchmarks Used: Evaluation was conducted on the IWLS-2005 benchmark suite and various RISC-V designs, along with a proprietary industrial benchmark of massive scale.

Implications

• Enhanced Hardware Efficiency: By offering superior AIG area reduction, SmaRTLy directly contributes to smaller, more power-efficient, and potentially faster integrated circuits, reducing manufacturing costs and improving device performance.
• Advancing RTL Synthesis: The approach pushes the boundaries of logic synthesis by demonstrating the tangible benefits of using advanced logic inferencing techniques to optimize fundamental structures like multiplexers.
• Benefit to RISC-V Ecosystem: Given its successful application on RISC-V benchmarks, SmaRTLy provides an immediate, proven optimization methodology that can be adopted by the burgeoning RISC-V community, leading to more highly optimized core implementations.
• Toolchain Development: SmaRTLy sets a new standard for optimization in the synthesis flow, potentially influencing the feature set and algorithms integrated into future commercial and open-source EDA tools.