Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality with At-MRAM Neural Engine

Abstract

Siracusa is a 16 nm heterogeneous RISC-V System-on-Chip designed for latency- and power-constrained Extended Reality (XR) applications requiring intensive Machine Learning. The key innovation is the tightly-coupled "At-Memory" integration of the N-EUREKA digital neural engine with on-chip MRAM Non-Volatile Memory (NVM), which significantly reduces the energy cost of accessing deep neural network weights. This architecture achieves 1.7x higher throughput and 3x better energy efficiency compared to standard XR SoCs that use NVM as background memory.

Report

Key Highlights

• Manufacturing and Application: Fabricated in 16 nm CMOS, Siracusa is optimized as a near-sensor, low-power heterogeneous SoC for next-generation Extended Reality (XR) applications.
• Core Innovation: The system features a novel "At-Memory" integration scheme, coupling the dedicated N-EUREKA digital neural engine directly with on-chip Magnetoresistive RAM (MRAM) NVM.
• Performance Leap: The tight coupling yields significant improvements, achieving 1.7x higher throughput and 3x better energy efficiency compared to existing XR SoCs that treat NVM as standard background memory.
• Architecture: The SoC combines a dedicated neural engine with a multi-core cluster of RISC-V processors for complex, mixed application workloads (ML, signal processing, and control).

Technical Details

• Fabrication Process: 16 nm CMOS technology.
• Target Constraints: Designed to meet stringent XR requirements: 10-20 ms end-to-end latency and low tens of mW average power consumption.
• Processing Units: Includes an octa-core cluster utilizing RISC-V Digital Signal Processing (DSP) cores.
• Neural Engine/Memory: Integrates the N-EUREKA digital neural engine tightly with MRAM (Magnetoresistive Memory) NVM.
• Measured Efficiency: The fabricated prototype achieves a peak energy efficiency of 8.84 TOp/J (Tera Operations per Joule) for DNN inference.
• Area Efficiency: Demonstrates an area efficiency of 65.2 GOp/s/mm².

Implications

• Advancing RISC-V in Edge AI: Siracusa demonstrates the capability of RISC-V based heterogeneous architectures to tackle highly demanding, power-constrained edge computing tasks like XR, validating RISC-V's role in future high-performance mobile AI silicon.
• Solving the NVM Bottleneck: By proving the effectiveness of "At-Memory" integration using MRAM, the paper provides a crucial blueprint for overcoming the severe power penalty associated with accessing large DNN weights from non-volatile memory, which is a key barrier to high-efficiency mobile ML acceleration.
• Enabling Future XR Devices: The exceptional energy efficiency (8.84 TOp/J) is essential for developing powerful, untethered XR/AR devices that rely on complex, millisecond-latency computer vision and machine learning without draining the battery rapidly.