Simulation Environment with Customized RISC-V Instructions for Logic-in-Memory Architectures

Abstract

Addressing the challenges of the memory wall, this work proposes using customized RISC-V instructions to support Logic-in-Memory (LiM) operations within computing architectures. The key innovation is a modular, cycle-accurate simulation environment developed using the gem5 simulator and enhanced GNU binary utilities. This testbed allows researchers to effectively evaluate potential LiM hardware and software co-designs.

Report

Key Highlights

• Targeting the Memory Wall: The research focuses on Logic-in-Memory (LiM) architectures to mitigate the bottleneck caused by costly data movement between CPU and memory in memory-hungry applications, such as machine learning.
• RISC-V Customization: The approach utilizes the custom extension capability inherent in the RISC-V Instruction Set Architecture (ISA) to integrate LiM operations directly into the executable code.
• Modular Testbed: The primary contribution is a comprehensive simulation environment designed to be a flexible testbed for evaluating diverse LiM solutions.
• Cycle-Accurate Simulation: The environment provides cycle-accurate simulation capabilities for the entire system, including the CPU and peripherals.

Technical Details

• Architecture Focus: Computation-in-Memory (CIM) or Logic-in-Memory (LiM) concepts are employed, typically leveraging emerging memory technologies for in-situ computation.
• Toolchain Modification: Standard GNU binary utilities are specifically enhanced to successfully generate RISC-V executables that incorporate the newly defined custom LiM operations.
• Simulation Platform: The simulation environment is built upon the widely-used gem5 system simulator, ensuring high fidelity and cycle-accurate performance analysis.
• Integration: The methodology includes integrating a user-defined, modular LiM module directly into the simulated system (CPU/peripherals) within the gem5 framework.

Implications

• Accelerated LiM Research: This simulation environment provides a critical infrastructure tool, allowing the research community to rapidly prototype and test various LiM hardware designs and instruction extensions without requiring expensive or lengthy hardware fabrication.
• Validation of RISC-V Extensibility: The work strongly demonstrates the practical benefits of the RISC-V ISA's custom extension feature, confirming its suitability for exploring radically different, non-Von Neumann computing paradigms like LiM.
• Co-design Enablement: By bridging the gap between hardware architecture (LiM module in gem5) and software (modified GNU toolchain), the testbed enables crucial co-design efforts necessary to maximize the performance and energy efficiency benefits of future computing architectures.