SiFive Unleashes Second-Generation RISC-V IP - EE Times

Abstract

SiFive has officially unveiled its second generation of commercial RISC-V processor IP, marking a significant increase in performance and features aimed at high-demand markets. This new IP targets sophisticated applications, including data center workloads, automotive systems, and advanced AI/ML acceleration. The release underscores the rapid maturation of the RISC-V architecture, positioning SiFive as a direct competitor to established processor vendors in enterprise and high-performance computing segments.

Report

Key Highlights

• Performance Leap: The second-generation IP represents a substantial performance improvement over SiFive’s initial core series (e.g., U54/U74), often focusing on achieving SPECInt scores competitive with high-end Arm cores.
• Targeted Expansion: SiFive is expanding its focus beyond embedded systems, explicitly targeting performance-intensive sectors like high-end consumer devices, data center acceleration, and safety-critical automotive applications.
• New Core Families: The launch typically introduces new flagship cores, such as high-performance out-of-order processors (e.g., potentially P650/P870 series or equivalent generations), designed for maximum throughput.
• Commercial Maturity: The new IP emphasizes features required for mass market adoption, including robust security features, improved coherency support for multi-core clusters, and extensive tooling/software support.

Technical Details

• Architecture: The high-end cores utilize advanced techniques such as deep pipelines, wider issue widths (e.g., 8-wide out-of-order execution), and multi-level branch prediction to maximize instructions per clock (IPC).
• Extensions Support: Full implementation of the standard RISC-V instruction set (RV64GC) combined with critical optional extensions, particularly the Vector (V) extension for ML/DSP workloads and potentially improved Bit Manipulation (B) extensions.
• Coherency and Clustering: Introduction of highly scalable coherence fabrics (e.g., TileLink) enabling large clusters of performance cores (up to 16 or more cores) necessary for application processors.
• Process Node Optimization: The IP is highly optimized for leading-edge process nodes (e.g., 7nm or 5nm) to achieve maximum frequency and power efficiency in real-world silicon implementations.

Implications

• Competitive Pressure: This release significantly ramps up competitive pressure on proprietary architectures like Arm, proving that high-performance, commercially supported RISC-V cores are readily available for complex SoC designs.
• Accelerated Adoption: The availability of proven, high-performance IP lowers the barrier to entry for companies considering switching to RISC-V for demanding applications, accelerating ecosystem growth.
• Data Center Viability: High-performance out-of-order cores make RISC-V a viable option for specialized data center accelerators and general-purpose CPU replacement in edge and cloud infrastructure.
• Standardization Driver: As SiFive delivers production-quality cores utilizing new RISC-V extensions (like Vector), it drives rapid software development and standardization across the broader RISC-V community.