SiFive details second generation RISC-V cores for AI accelerators ... - eeNews Europe

Abstract

SiFive has announced details regarding its second generation of RISC-V cores specifically optimized for deployment within high-performance AI accelerators. This new product generation signals SiFive's strategy to capture the lucrative machine learning and deep learning hardware market using the open-source instruction set architecture. These improved cores are expected to deliver significant performance and efficiency gains required for modern AI workloads compared to the previous generation.

Report

SiFive Second Generation RISC-V Cores for AI Accelerators

Key Highlights

• Architectural Upgrade: SiFive is launching its second generation of high-performance RISC-V core IP.
• Target Market: The primary focus for these new cores is high-efficiency AI accelerators, deep learning inference, and specialized computing applications.
• Vendor Leadership: This release reinforces SiFive's position as a leading commercial provider of high-quality, specialized RISC-V core IP.
• Performance Focus: The cores are designed to meet the demanding requirements of parallel processing and vector computation inherent in AI tasks.

Technical Details

• Vector Processing Enhancement: While specific details are not provided in the snippet, a second-generation AI-focused core likely features substantial improvements to the implementation of the RISC-V Vector (RVV) extension for wider vector lanes and greater parallelism.
• Efficiency: Optimization for power efficiency (performance per watt) is crucial, indicating advanced microarchitecture tuning for lower latency and higher throughput during matrix operations.
• Clustering Capabilities: The cores are likely designed to be deployed in large clusters or tile arrays, requiring sophisticated cache coherence mechanisms and inter-core communication fabrics suitable for massive parallel processing needed in accelerators.
• Custom Instruction Support: SiFive likely offers or supports custom extensions tailored to specific neural network operators, enhancing performance beyond the standard RISC-V ISA.

Implications

• RISC-V Maturity: The introduction of a dedicated second-generation product line for a specific, demanding workload like AI demonstrates the increasing maturity and commercial viability of the RISC-V architecture.
• Competition with Proprietary ISAs: This move directly intensifies competition with established proprietary architectures (like Arm's specialized compute IP) in the fastest-growing segment of the semiconductor industry.
• Acceleration of AI Hardware Innovation: By providing high-performance, optimized, and licensed cores, SiFive lowers the barrier for companies seeking to design custom AI chips, accelerating overall innovation in the hardware ecosystem.
• Ecosystem Growth: Success in the AI accelerator market validates the flexibility of RISC-V, encouraging further investment from tool vendors, software developers, and chip designers across the ecosystem.