Abstract

This work introduces a scalable, 28nm integrated circuit implementation of a coupled oscillator network designed to efficiently simulate complex dynamical systems for applications like analog computing and transport network stability analysis. The chip utilizes a clustered architecture of modified Phase-Locked Loops (PLLs) that feature programmable coupling mechanisms, allowing dynamic tuning of network topology and complexity. The inclusion of an integrated RISC-V processor enables algorithmic control over the network dynamics, providing a practical hardware alternative to computationally intensive software simulations.

Report

Analysis Report: Scalable 28nm Coupled Oscillator Network IC

Key Highlights

• Novel Hardware Solution: A scalable, 28nm integrated circuit (IC) implementation of a coupled oscillator network is presented.
• Tunability: The architecture features the ability to flexibly vary the network topology and a complexity parameter during operation.
• Target Applications: Developed to address the computational intensity of simulating large oscillator networks used for analogue computing (e.g., optimization tasks) and stability analysis of transport networks (e.g., power grids).
• Integrated Control: The IC incorporates a RISC-V processor to enable future algorithmic implementations and control of the network dynamics.

Technical Details

• Process Technology: Implemented using a 28nm IC fabrication process.
• Core Component: The oscillators are built using modified integrated Phase-Locked Loops (PLLs).
• Architecture: Employs a clustered, brain-inspired architecture to achieve scalability.
• Cluster Composition: Each cluster within the network contains 7 PLLs.
• Coupling Mechanism: Features programmable coupling mechanisms between oscillators.
• Functionality: Designed to provide a practical alternative for large-scale network simulations in fields where systems are run near or need to avoid critical dynamic states.

Implications

• Acceleration of Analog Computing: Provides a dedicated, high-efficiency hardware platform for simulating complex dynamical systems, offering a major speedup compared to traditional digital simulations of large coupled oscillator networks.
• RISC-V as Control Fabric: The integration of a RISC-V core is crucial, positioning it as the necessary control layer for managing emerging, highly specialized analog computing hardware. This ensures that the complex physical dynamics can be precisely governed by standard, flexible software algorithms.
• System Co-design: This implementation enables researchers to co-optimize physical network dynamics (topology, complexity) with digital algorithms running on the embedded RISC-V processor, accelerating the development of novel analog computing methods.
• Broad Research Utility: The tunable nature makes this IC a powerful experimental tool for research into both computational optimization and complex system stability analysis (e.g., power grid resilience).