Abstract

Safety-critical systems utilizing powerful multicores must rigorously validate mutual interference arising from shared hardware resources. This paper introduces significant enhancements to the SafeTI traffic injector, including internal pipelining for higher-rate injection and adaptability for multiple interfaces. These improvements facilitate effective, otherwise untestable, interference testing within a powerful heterogeneous RISC-V multicore based on Gaisler's technology for the demanding space domain.

Report

SafeTI Traffic Injector Enhancement Report

Key Highlights

• Critical Domain Focus: The work targets interference testing crucial for safety-critical domains like automotive, space, and robotics, which are increasingly adopting complex multicore architectures.
• SafeTI Enhancement: The existing SafeTI traffic injector has been significantly enhanced to improve its capability and fidelity.
• High-Rate Injection: A key architectural improvement is the introduction of internal pipelining to enable higher-rate traffic injection for more effective stress testing.
• RISC-V Integration: The enhanced injector is integrated into a more powerful, heterogeneous RISC-V multicore platform.
• Space Application: The target deployment platform leverages Gaisler’s technology, specifically positioning this solution for the space domain.

Technical Details

• Base Tool: The SafeTI traffic injector is a specialized hardware solution designed to test mutual interference casuistics that cannot be validated using software-only methods.
• Performance Upgrade: Internal pipelining was implemented within the SafeTI hardware logic to increase the maximum injection rate of interfering traffic onto shared resources.
• Versatility: The injector was tailored to interface with multiple hardware interfaces, increasing its applicability across various system-on-chip (SoC) components.
• Target Architecture: The final system utilizes a heterogeneous RISC-V multicore, indicating a complex blend of core types and shared resources requiring advanced interference validation.
• Vendor Technology: The implementation specifically relies on Gaisler’s technology, which is well-established in high-reliability, radiation-hardened computing environments.

Implications

• Enabling Critical RISC-V Adoption: Providing robust, hardware-assisted validation tools like the enhanced SafeTI is essential for proving the dependability and predictability required for RISC-V multicore adoption in highly regulated safety-critical markets (e.g., ISO 26262 for automotive, DO-254/DO-178C for avionics/space).
• Hardware-Assisted Validation: This work emphasizes the limitation of purely software-based testing for temporal interference in multicores, demonstrating the necessity of dedicated hardware injectors for effective worst-case execution time (WCET) analysis and certification.
• Ecosystem Specialization: The integration with Gaisler technology highlights RISC-V's maturity and customization potential in niche, high-value sectors like space computing, where fault tolerance and reliable interference testing are paramount concerns.