SafeLS: Toward Building a Lockstep NOEL-V Core

Abstract

This paper presents SafeLS, an extension designed to integrate lockstep capabilities into Gaisler's NOEL-V RISC-V core for use in safety-critical systems. Lockstep architecture is employed to prevent Common Cause Failures (CCFs) by ensuring that redundant cores execute the same instructions with time staggering, preventing simultaneous identical states. This modification allows the detection of random hardware errors caused by radiation and other electromagnetic interference through comparison of the staggered states.

Report

Key Highlights

• Safety Focus: The work targets highly reliable operation in safety-critical systems, including automotive, avionics, and space applications.
• Fault Mitigation: The primary goal is to prevent Silent Data Corruption (SDC) caused by random hardware errors (e.g., radiation, electromagnetic interference).
• CCF Prevention: The technique specifically combats Common Cause Failures (CCFs), where a single fault causes identical, and therefore undetectable, errors in redundant elements.
• Core Modification: The paper details the extension of Gaisler's RISC-V NOEL-V core to incorporate lockstep functionality, resulting in the design named SafeLS.

Technical Details

• Redundancy Scheme: Uses dual-core lockstep execution.
• Mechanism: Two independent cores execute the identical flow of instructions.
• Time Staggering: State comparison is made possible by deliberately introducing a time offset (staggering) between the execution states of the two cores.
• Purpose of Staggering: This temporal difference ensures the states are never identical simultaneously, ensuring that a single fault leads to different errors in the redundant elements, which are then detectable by comparison.
• Target Architecture: The implementation is built upon Gaisler's NOEL-V, a RISC-V processor core.

Implications

• RISC-V Ecosystem Maturity: The integration of robust, lockstep fault tolerance helps mature the RISC-V ecosystem, making it a validated candidate for high-assurance and functional safety applications (e.g., those requiring high Safety Integrity Levels).
• Commercial Viability: By providing a solution to avoid critical hardware failures in harsh environments, SafeLS enhances the appeal and trustworthiness of the NOEL-V core, especially for aerospace and defense sectors.
• Enabling Harsh Environments: This work facilitates the deployment of RISC-V processors in environments prone to radiation effects and Single Event Upsets (SEUs), such as deep space missions or critical terrestrial infrastructure.