RVCoreP : An optimized RISC-V soft processor of five-stage pipelining

Abstract

RVCoreP is an optimized five-stage pipelined soft processor designed for FPGAs, implementing the RISC-V 32-bit Integer (RV32I) instruction set architecture. The processor incorporates three key optimization techniques focusing on instruction fetch/branch prediction, ALU performance, and data memory handling. Evaluation results demonstrate that RVCoreP achieves a significant 30.0% performance improvement compared to the high-performance open-source VexRiscv processor.

Report

RVCoreP : An optimized RISC-V soft processor of five-stage pipelining

Key Highlights

• Processor Name: RVCoreP, an optimized soft processor implementation of the RISC-V RV32I instruction set.
• Architecture: Utilizes a five-stage pipelining architecture for improved performance on FPGAs.
• Performance Gain: Demonstrated 30.0% performance improvement over the comparable high-performance open-source processor, VexRiscv.
• Implementation: The design was implemented using Verilog HDL.
• Verification: Verified through simulation and deployment on an actual Xilinx Atrix-7 FPGA board.

Technical Details

• Target ISA: RISC-V RV32I (the basic 32-bit integer instruction set).
• Core Architecture: Five-stage pipeline.
• Optimization Method 1: Instruction fetch unit optimization, which specifically includes a pipelined branch prediction mechanism to minimize pipeline stalls.
• Optimization Method 2: Optimization of the Arithmetic Logic Unit (ALU).
• Optimization Method 3: Data alignment and sign-extension optimization applied to the data memory output.
• Evaluation Metrics: The processor was evaluated based on standard metrics including IPC (instructions per cycle), maximum operating frequency, hardware resource utilization, and overall processor performance.

Implications

• FPGA Soft Core Viability: The work demonstrates that significant performance boosts are achievable in cost-effective, loyalty-free RISC-V soft processors suitable for embedded systems running on FPGAs.
• Competitive Benchmark: By surpassing VexRiscv by 30.0%, RVCoreP sets a new high-water mark for performance efficiency within the open-source RV32I soft core landscape.
• Architectural Contribution: The specific optimization techniques, particularly the integration of pipelined branch prediction into the five-stage soft core design, provide valuable architectural insights and improvements that can be leveraged by the broader RISC-V open-source community.