RVCoreP-32IM: An effective architecture to implement mul/div instructions for five stage RISC-V soft processors

Abstract

The RVCoreP-32IM architecture is proposed as an effective extension to the five-stage RVCoreP soft processor to efficiently implement the RISC-V M-extension (multiplication/division instructions). Utilizing a simple fork-join method to expand execution capability, the design quantifies the performance benefit of adding multiplication and division support. Benchmark results demonstrate that RV32IM improves performance by up to 3.13 times over the RV32I baseline, proving 13% better than comparable equivalent RISC-V processors.

Report

Key Highlights

• Architectural Target: A five-stage RISC-V soft processor, specifically extending the existing RVCoreP core.
• Innovation: Introduction of the RVCoreP-32IM architecture to integrate the RISC-V M-extension (multiplication and division instructions).
• Performance Improvement: The RV32IM implementation showed a 1.87 times performance increase when using a radix-4 multiplier and a 3.13 times increase using a DSP multiplier, relative to the RV32I baseline.
• Competitive Efficiency: The proposed RV32IM implementation offers 13% better overall performance compared to an equivalent existing RISC-V processor.

Technical Details

• Base Instruction Set: RV32I (Basic 32-bit Integer Instruction Set).
• Extension Implemented: M-extension (Multiplication and Division).
• Implementation Strategy: A "simple fork-join method" is employed to expand the processor's execution capability, allowing for modular enhancement and M-extension support.
• Evaluation Metrics: Benchmarking was conducted using industry-standard programs: Dhrystone, Coremark, and Embench.
• Hardware Variants Tested: Performance analysis included configurations utilizing both radix-4 multipliers and dedicated DSP multipliers.

Implications

• Informed Design Decisions: The paper addresses the crucial question of when and how much performance gain justifies adding the M-extension to soft processors, providing essential data for RISC-V developers targeting embedded systems.
• High-Efficiency Reference: RVCoreP-32IM establishes a high-efficiency reference architecture for implementing M-extension instructions within constrained five-stage pipeline designs.
• RISC-V Ecosystem Advancement: By demonstrating significant performance boosts with a quantified cost-benefit analysis, the work encourages the broader adoption of optimized RV32IM cores in performance-critical embedded applications where multiplication/division is frequent.