Abstract

This paper proposes RVCoreP-32IC, a high-performance RISC-V soft processor targeting FPGAs, featuring a novel instruction fetch unit engineered to efficiently support compressed instructions (RVC). Although RVC reduces code size by about 25%, it traditionally complicates fetch logic and severely impacts performance, a limitation the proposed unit overcomes. Benchmarks confirm the success of this design, showing the RVCoreP-32IC achieving 42.5% higher DMIPS and 41.1% higher CoreMark values compared to related soft processor implementations.

Report

RVCoreP-32IC Technical Report

Key Highlights

• Processor Innovation: The proposal details RVCoreP-32IC, a high-performance RISC-V soft processor optimized for Field-Programmable Gate Arrays (FPGAs).
• Core Feature: The primary innovation is an efficient instruction fetch unit that fully supports the RISC-V Compressed Instructions (RVC) extension while maintaining high execution speed.
• Performance Uplift: The RVCoreP-32IC demonstrated significant performance gains compared to related works, achieving 42.5% higher DMIPS and 41.1% higher CoreMark scores.
• Hardware Verification: The design was implemented and verified on an actual Xilinx Artix-7 FPGA board.

Technical Details

• Instruction Set Focus: The design specifically addresses the complexity introduced by the RISC-V compressed instruction extension (RVC), which typically reduces program size by approximately 25% but complicates the instruction fetch pipeline.
• Architecture: The core uses a specialized instruction fetch unit designed to handle the variable-length nature of compressed instructions without incurring severe performance penalties.
• Implementation: The soft processor was implemented using Verilog HDL.
• Benchmark Results: The processor's performance metrics were reported as:
  • DMIPS: 42.5% higher than related work.
  • CoreMark: 41.1% higher than related work.
  • Embench: 21.3% higher than related work.

Implications

• Soft Processor Viability: RVCoreP-32IC significantly raises the performance benchmark for soft RISC-V cores implemented on FPGAs, making soft solutions more competitive against hard IP cores for embedded applications.
• RVC Adoption: By mitigating the performance cost historically associated with RVC's fetch complexity, this design encourages wider adoption of compressed instructions, allowing developers to benefit from smaller code footprints (reduced memory usage) without the typical performance sacrifice.
• FPGA Ecosystem: The availability of high-performance, open-source-friendly cores like RVCoreP-32IC accelerates prototyping and development within the FPGA and embedded RISC-V ecosystem, especially for power- or area-constrained designs where code density is critical.