Roadmap for Open-Source Chiplet-Based RISC-V Systems For HPC and AI (ETH Zurich, Univ. of Bologna) - Semiconductor Engineering

Abstract

Researchers from ETH Zurich and the University of Bologna have proposed a definitive roadmap for creating next-generation HPC and AI systems based entirely on open-source RISC-V processors and modular chiplet architectures. This strategy leverages the flexibility of chiplets to integrate diverse functions (e.g., compute, memory, accelerators) and utilizes the open nature of RISC-V to foster innovation and customization. The goal is to democratize high-performance silicon design, making scalable, specialized computing accessible to a wider community.

Report

Roadmap for Open-Source Chiplet-Based RISC-V Systems

Key Highlights

• Open Roadmap Initiative: The project outlines a plan for developing sophisticated computing systems explicitly targeting High-Performance Computing (HPC) and Artificial Intelligence (AI) acceleration.
• Core Technologies: The architecture is built upon the open instruction set architecture (ISA) of RISC-V combined with modular chiplet design principles.
• Institutional Leadership: The roadmap is being driven by collaboration between leading academic institutions, notably ETH Zurich and the University of Bologna.
• Democratization of Silicon: The ultimate goal is to reduce reliance on proprietary silicon and enable scalable, customized compute solutions through open standards and accessible hardware.
• Target Market: The focus is on creating power-efficient, highly scalable solutions suitable for data centers and specialized computational tasks.

Technical Details

• Chiplet Architecture: The design relies on heterogeneous integration, where specialized compute units (e.g., RISC-V cores, custom AI accelerators, memory controllers) are manufactured as separate dies (chiplets) and connected via a high-speed inter-die interconnect.
• Scalability: Chiplets provide inherent advantages in scaling core counts and integrating diverse technologies/process nodes that would be economically or physically challenging in a monolithic system-on-chip (SoC).
• RISC-V Focus: Utilization of high-performance RISC-V cores capable of supporting necessary extensions, particularly vector processing (critical for HPC) and custom instructions (crucial for AI/ML acceleration).
• Open Interconnect: A crucial element of the roadmap involves establishing an open standard for die-to-die communication to ensure interoperability among chiplets sourced from different providers or designers.

Implications

• Validation of RISC-V: This initiative significantly strengthens the perception of RISC-V as a viable, long-term architecture not just for embedded systems, but for the most complex and demanding HPC and AI applications.
• Accelerated Innovation: By providing an open hardware platform utilizing chiplets, academics, startups, and smaller firms can rapidly prototype and integrate specialized accelerators without needing access to expensive, complex monolithic fabrication processes.
• Supply Chain Flexibility: Open-source chiplet designs foster a more resilient and distributed hardware supply chain, reducing reliance on proprietary vendors for critical components.
• Future Standardization: The roadmap drives industry momentum toward standardized open interfaces (like potentially leveraging or influencing standards like UCIe) for modular computing, fostering an ecosystem where components from multiple vendors can be mixed and matched.