RISE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Encryption

Abstract

RISE is a novel RISC-V System-on-Chip (SoC) designed to accelerate critical message-to-ciphertext conversion operations for Homomorphic Encryption (HE) on resource-constrained edge devices. The architecture overcomes bottlenecks in error sampling and Number Theoretic Transform (NTT) via a lightweight pseudo-random number generator and scalable data-level parallelism within a unified en/decryption datapath. Evaluation demonstrates that RISE achieves a massive energy efficiency gain, up to 6191.19X, compared to a baseline RISC-V processor performing the same encryption tasks.

Report

Key Highlights

• Target Application: Acceleration of Homomorphic Encryption (HE) conversion operations (en/decryption and error sampling) specifically on edge devices to enhance data privacy.
• Bottleneck Identification: Profiling identified error sampling, encryption, and decryption (specifically the Number Theoretic Transform - NTT) as the main bottlenecks in edge-side HE conversion.
• Energy Efficiency Gain: The RISE SoC delivers exceptional energy efficiency improvements, achieving up to 6191.19X more energy efficiency for message-to-ciphertext conversion and 2481.44X for ciphertext-to-message conversion compared to a pure RISC-V processor implementation.
• Area Optimization: The design utilizes a unified en/decryption datapath to minimize required chip area.

Technical Details

• Architecture: RISE is a complete RTL design featuring a standard RISC-V processor interfaced with a custom hardware accelerator core.
• Error Sampling Acceleration: Utilizes a custom, area-efficient, and lightweight pseudo-random number generator (PRNG) core combined with fast sampling techniques.
• Encryption/Decryption Acceleration: Accelerates the core operation, the Number Theoretic Transform (NTT), by implementing scalable, data-level parallelism.
• Memory Management: The design efficiently exploits memory reuse and data reordering techniques to utilize a minimal amount of on-chip memory, which is crucial for edge deployment.

Implications

• Practical HE on the Edge: RISE addresses a significant gap in HE research by focusing on the often-overlooked edge-side conversion steps, making high-privacy cryptographic solutions practical for IoT and edge computing environments.
• RISC-V Ecosystem Expansion: This work showcases the power of RISC-V's extensibility, demonstrating how custom hardware accelerators can be seamlessly integrated with standard RISC-V cores to solve highly specialized, computation-intensive problems in cryptography.
• Security and Privacy: By enabling highly efficient HE implementation directly on the edge, RISE mitigates security and privacy risks associated with uploading raw, unencrypted user data to the cloud for processing.
• Energy/Performance Benchmark: The measured energy efficiency improvements establish a new benchmark for accelerating complex lattice-based cryptography on resource-constrained devices.