Abstract

This article introduces and evaluates specific word-size modular arithmetic instructions designed for the RISC-V Instruction Set Architecture (ISA) to significantly enhance the software implementation of Residue Number Systems (RNS), which are critical for high-performance DSP and cryptography. Simulations using the GEM5 platform show that integrating these instructions, particularly with the Kawamura base extension algorithm, yields substantial performance gains over conventional methods. The proposed RISC-V implementation requires 4.5 times less cycles in In Order processors and 8 times less cycles in Out of Order processors compared to optimized x86 architectures.

Report

RISC-V Word-Size Modular Instructions for Residue Number Systems

Key Highlights

• Core Innovation: Proposal of specific word-size modular arithmetic instructions tailored for the RISC-V ISA to accelerate Residue Number Systems (RNS) computations in software.
• Performance Gain: RNS modular multiplication saw a speedup of 2.76 times (In Order processors) and more than 3 times (Out of Order processors) compared to implementations using pseudo-Mersenne moduli.
• Competitive Advantage: Compared directly to x86 architectures, the RISC-V implementation with specific instructions requires 4.5 times less cycles in In Order systems and 8 times less cycles in Out of Order systems.
• Algorithm Optimization: The fastest RNS modular multiplication sequential algorithm tested was the Kawamura et al. base extension.

Technical Details

• Target Domain: Residue Number Systems (RNS), utilized in high-performance digital signal processing (DSP) and cryptographic applications.
• Instruction Focus: The research evaluates the impact of novel word-size modular arithmetic instructions added to the RISC-V ISA, overcoming the limitations imposed by the rigid ISAs of market-dominant microprocessors (e.g., x86).
• Evaluation Method: Performance was measured via simulation of various RNS modular multiplication sequential algorithms.
• Simulation Environment: Architectures were simulated using the GEM5 simulator, assessing performance on both In Order and Out of Order processor models.
• Optimal Algorithm: The specific algorithms benchmarked included the Kawamura et al. base extension, which proved to be the most efficient implementation using the new instructions.

Implications

• RNS Adoption: By providing high-performance RNS support directly via software instructions, the technology removes the rigidity of conventional ISAs as a barrier, enabling broader use of RNS outside of highly specialized hardware.
• RISC-V Extensibility Validation: The results strongly validate the RISC-V philosophy, demonstrating how custom extensions can create highly efficient, domain-specific acceleration (modular arithmetic) that outperforms legacy architectures like x86 by substantial margins.
• Cryptographic Acceleration: The significant acceleration in modular arithmetic is crucial for cryptographic primitives, potentially making RISC-V the architecture of choice for software-based high-speed crypto and number theory computation.
• Standardization Potential: This work advocates for the inclusion of specialized modular instructions, which could lead to a standard extension for high-performance computing within the future RISC-V specification.