RISC-V V Vector Extension (RVV) with reduced number of vector registers

Abstract

This work proposes reducing the area overhead of the RISC-V V Vector Extension (RVV) specifically for use in small processors. The innovation is centered on reducing the standard 32 vector registers to 16 or 8 registers while retaining other RVV features. Although this modification prevents binary code compatibility with standard RVV cores, it maintains high utilization for specific tasks like signal processing through simple compiler parameterization.

Report

Key Highlights

• Area Reduction Focus: The primary goal is to significantly reduce the silicon area footprint of the RVV extension for implementation in small processors.
• Register Count Reduction: The standard requirement of 32 vector registers is proposed to be reduced to either 16 or 8 vector registers.
• Compiler Parameterization: While binary compatibility with standard RVV is lost, the change does not require a new programming model; it is handled by parameterizing the register file size within the compiler.
• Efficiency for Specialized Kernels: The reduced vector file still achieves high utilization for relevant workloads, such as signal processing kernels, demonstrating efficiency even at a 1:4 chaining ratio.

Technical Details

• Standard Specification: The baseline RVV specification requires a Vector Register File containing 32 vector registers.
• Proposed Configurations: Implementations are explored with register counts reduced by half (16 registers) or by three-quarters (8 registers).
• Compatibility Status: Cores implementing the reduced register set are not binary code compatible with standard 32-register RVV implementations.
• Software Adaptation: Toolchains must be updated to accept and utilize parameters defining the specific reduced size of the vector register file ($V{R}=16$ or $V{R}=8$).

Implications

• Enabling Constrained Computing: This modification significantly lowers the barrier to entry for integrating vector processing capabilities into deeply embedded systems and small microcontroller units where area constraints are paramount.
• Design Flexibility (PPA Trade-off): It provides hardware designers increased flexibility to trade maximum performance for reduced silicon area and potentially lower power consumption, optimizing the processor for specific cost-sensitive applications.
• Market Expansion: By demonstrating high efficiency for specific low-register-count operations (like DSP), the proposal validates the use of RVV in specialized fields that previously might have avoided it due to hardware overhead.