RISC-V: Shaping the Future of Mobility with Open Standards - EE Times

Abstract

RISC-V is emerging as the essential open standard architecture driving the future of mobility, specifically targeting advanced automotive applications like ADAS and high-performance computing in vehicles. The modular and customizable nature of the RISC-V Instruction Set Architecture (ISA) addresses the automotive sector’s critical need for specialization, functional safety compliance (e.g., ISO 26262), and cost reduction. This transition marks a significant shift away from proprietary solutions, fostering industry collaboration and accelerating the development cycle for next-generation transportation technologies.

Report

RISC-V: Shaping the Future of Mobility with Open Standards

Key Highlights

• Foundational Open Standard: RISC-V is positioned as the dominant open standard ISA required for the development of future high-performance and safety-critical mobility solutions.
• Automotive Customization: The architecture’s inherent extensibility allows OEMs and Tier 1 suppliers to design highly customized silicon tailored precisely for specialized workloads, such as sensor fusion, real-time control, and AI acceleration.
• Functional Safety Focus: The RISC-V community is actively developing profiles and extensions specifically engineered to meet stringent automotive functional safety standards (up to ASIL D), ensuring reliability for mission-critical systems.
• Vendor Independence: Adoption accelerates freedom from proprietary licensing fees and vendor lock-in, significantly reducing the bill of materials (BOM) for high-volume markets like Electric Vehicles (EVs).

Technical Details

• Specialized Cores: The mobility sector utilizes RISC-V for a variety of tasks, ranging from small, low-power microcontrollers managing vehicle subsystems to high-core-count clusters handling complex ADAS computation.
• ISA Extensions for Mobility: Efforts are underway to standardize specialized vector and custom instruction extensions that enhance performance for crucial automotive algorithms, including image processing and cryptography.
• Hardware/Software Co-Design: RISC-V enables seamless co-design approaches necessary for achieving ASIL compliance, utilizing features like Physical Memory Protection (PMP) and robust exception handling mechanisms.
• Heterogeneous Computing: RISC-V cores are integral to heterogeneous SoCs, acting as control planes or managing peripherals alongside proprietary accelerators (like GPUs or dedicated NPUs) for maximizing power efficiency.

Implications

• Ecosystem Validation: The deep integration of RISC-V into the automotive pipeline validates its maturity and long-term viability, attracting massive investment in verification tools, reference designs, and operating system support (including automotive-grade Linux and RTOSs).
• Decentralization of Supply Chain: By promoting an open standard, RISC-V enhances supply chain resilience, allowing multiple vendors to produce compatible hardware and reducing geographical dependence on single-source suppliers.
• Accelerated Innovation: Eliminating the barrier of proprietary architecture licensing lowers the entry cost for startups and established players alike, fostering quicker iteration and innovation in automotive software and hardware platforms.
• Competition and Pricing: Widespread adoption in mobility increases competitive pressure on traditional proprietary ISA providers, potentially driving down costs across the semiconductor industry.