RISC-V processor enhanced with a dynamic micro-decoder unit

Abstract

This paper assesses the benefits and costs of integrating a CISC-inspired dynamic micro-decoding unit into a standard RISC-V processor core. The unit is designed to sit within a specific pipeline stage, enabling the dynamic execution of custom instruction sequences. This enhancement aims to improve system security and energy efficiency, supporting advanced features like binary compression and behavior obfuscation.

Report

Key Highlights

• The research evaluates the integration of a dynamic micro-decoding unit, inspired by CISC architectures, into an open-source RISC-V processor core.
• The primary goal is to address modern design constraints, specifically enhancing security and energy efficiency alongside execution speed.
• This specialized unit facilitates the dynamic execution of custom instruction sequences.
• Targeted applications for the custom sequences include binary compression and software behavior obfuscation.

Technical Details

• Target Architecture: RISC-V core (representing mature RISC architecture).
• Integrated Component: A dynamic micro-decoding unit.
• Design Inspiration: CISC processors.
• Placement: The unit is integrated within a "specific pipeline stage" of the RISC-V core.
• Functionality: Translates custom input into instruction sequences dynamically.

Implications

• Architectural Blending: This work represents an increasing maturity in RISC design, where architects are willing to integrate complex, performance-boosting elements traditionally found in CISC processors.
• Enhanced Customization and Security: The ability to execute dynamic custom instruction sequences provides RISC-V users with powerful tools for hardware-assisted obfuscation, significantly boosting security features at the core level.
• Efficiency Gains: The proposed system offers routes to improve energy efficiency and performance through techniques like binary compression, making RISC-V competitive in low-power and specialized computing domains.