RHS-TRNG: A Resilient High-Speed True Random Number Generator Based on STT-MTJ Device

Abstract

The RHS-TRNG is a novel True Random Number Generator utilizing the stochastic switching characteristics of Spin-Transfer Torque Magnetic Tunnel Junction (STT-MTJ) devices to deliver high-quality randomness. This design achieves exceptional speed, reaching up to 303 Mb/s per cell—the highest among existing MTJ-based TRNGs—while ensuring strong resilience against PVT variations through structural innovations. Integrated into a RISC-V processor via customized instructions, the system demonstrated a significant 3.4 to 12x performance speedup for applications requiring intensive random number generation compared to software implementations.

Report

RHS-TRNG: A Resilient High-Speed True Random Number Generator Based on STT-MTJ Device

Key Highlights

• Novel Technology Base: The RHS-TRNG leverages the stochastic switching behavior of Spin-Transfer Torque Magnetic Tunnel Junction (STT-MTJ) devices as its core entropy source.
• Record Speed: A single cell of the RHS-TRNG achieves a random bit generation speed of up to 303 Mb/s, which is reported as the highest throughput among existing MTJ-based TRNG designs.
• High Resilience: The design features enhanced resilience against Process, Voltage, and Temperature (PVT) variations, achieved through the use of bidirectional switching currents and a dual generator unit architecture.
• System Integration: The TRNG is implemented using a circuit/system co-design approach, integrating it into a RISC-V processor as an acceleration component.
• Significant Performance Gain: System evaluations using the gem5 simulator showed that the RHS-TRNG acceleration component provides a 3.4x to 12x performance improvement when speeding up demanding applications, such as option pricing programs, compared to software-based random number generation.

Technical Details

Implications

This research carries significant implications for the RISC-V ecosystem and the broader field of hardware security and specialized acceleration:

• Enhancing RISC-V Security and Performance: Integrating the RHS-TRNG directly into the RISC-V core via custom instructions demonstrates the power of the RISC-V ISA to incorporate specialized, high-performance hardware modules. This provides a fast, dedicated source of high-quality entropy critical for cryptographic operations, secure boot, and key generation.
• Accelerating Stochastic Applications: The proven 3.4-12x performance boost for workloads like financial simulation (option pricing) highlights how integrated TRNGs can unlock major efficiency gains in domains heavily reliant on Monte Carlo methods, making RISC-V processors more competitive in HPC and data analytics.
• Advancing Spintronics/MTJ Integration: By utilizing STT-MTJ devices, this work pushes the boundaries of using emerging non-volatile memory technologies (MRAM/MTJ) not just for storage, but as fundamental components for essential computing functions like true random number generation, signaling a shift toward more unified memory and logic architectures.
• Hardware Resilience: The focus on resilience against PVT variations addresses a major barrier for adopting high-speed, non-CMOS entropy sources, ensuring that the TRNG remains reliable across various operating conditions and manufacturing variability.