Reconfigurable Edge Hardware for Intelligent IDS: Systematic Approach

Abstract

This paper addresses the deployment of intelligent Intrusion Detection Systems (I-IDS) on resource-constrained Edge hardware by proposing a systematic approach utilizing reconfigurable FPGA technology. The authors implemented and compared two architectures: a purely FPGA-based Dataflow Processor (DFP) and a co-designed system featuring a RISC-V soft-core Processor (SCP). Results confirm that both designs are suitable for Edge applications in terms of resource and energy efficiency, with the DFP significantly outperforming state-of-the-art solutions for high-speed security applications.

Report

Key Highlights

• Systematic Approach to I-IDS: The paper introduces a systematic method for constructing Intelligent Intrusion Detection Systems (I-IDS) specifically tailored for reconfigurable Edge hardware.
• Reconfigurable Hardware Focus: The implementation targets state-of-the-art Field Programmable Gate Arrays (FPGAs) to handle the resource constraints and dynamic nature of Edge setups.
• Dual Architecture Comparison: Two distinct architectures were implemented and compared: a purely FPGA-based Dataflow Processor (DFP) and an FPGA-based Soft-Core Processor (SCP) utilizing a RISC-V soft-core.
• Performance Superiority: The DFP implementation demonstrated clear performance superiority, outperforming State-of-the-Art (SoA) systems while maintaining low hardware costs.
• Suitability for Edge: Both proposed solutions (DFP and SCP) prove suitable for high-speed Edge applications due to their high energy efficiency and low hardware resource footprint.

Technical Details

• Target Domain: Intelligent Intrusion Detection Systems (I-IDS) leveraging Machine Learning for anomaly detection in network communication.
• Implementation Platform: State-of-the-art FPGAs.
• Architecture 1 (DFP): A fully customized, high-performance Dataflow Processor realized purely in FPGA logic, optimized for throughput and efficiency in the IDS task.
• Architecture 2 (SCP): A co-designed approach where a RISC-V soft-core processor manages tasks alongside specialized hardware acceleration within the FPGA fabric.
• Metrics: The evaluation focused on hardware resource utilization, energy efficiency, and required performance for modern, high-speed communication technologies.

Implications

• Validation of RISC-V in Security: The use of a RISC-V soft-core (SCP) explicitly validates the ISA's utility in deploying complex, ML-based security systems on resource-constrained reconfigurable platforms, strengthening its presence in the Edge computing and security domain.
• Hardware Acceleration Roadmap: The comparative success of the DFP over the RISC-V SCP approach (while both were efficient) emphasizes that for maximum performance in high-speed network security, dedicated dataflow acceleration remains superior, guiding future RISC-V-based heterogeneous system designs toward dedicated accelerators.
• Edge Security Advancement: This systematic approach enables the creation of highly performant, low-cost IDS solutions essential for securing modern decentralized and resource-limited communication infrastructure (e.g., IoT and 5G Edge deployments), where traditional software solutions struggle with latency and throughput requirements.