Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications

Abstract

Quadrilatero is an open-source RISC-V programmable matrix coprocessor designed to optimize AI workloads in low-power edge applications. It utilizes a systolic array architecture and a streamlined matrix ISA extension to overcome the limitations of traditional vector processors during matrix multiplication (MatMul). Post-synthesis results in 65-nm technology demonstrate high FPU utilization (99.4%) and significantly improved area efficiency (up to 77%) and energy efficiency (up to 15%) compared to competing RISC-V processors.

Report

Quadrilatero: A RISC-V programmable matrix coprocessor

Key Highlights

• Core Innovation: An open-source, programmable RISC-V coprocessor designed specifically as a systolic array accelerator for matrix computations (MatMul).
• Target Application: Low-power edge devices and AI-based Internet-of-Things (IoT) applications.
• Performance: Achieves exceptional utilization, reaching up to 99.4% of FPU utilization.
• Efficiency Gains: Compared to state-of-the-art open-source RISC-V vector and hybrid vector-matrix processors, Quadrilatero shows up to 77% improvement in area efficiency and 15% improvement in energy efficiency.
• Solution Rationale: Developed to address the inherent inefficiency of vector processors in matrix computations, which stem from limited parallelism and expensive access to the Vector Register File (VRF).

Technical Details

• Architecture: Systolic array coprocessor, offering optimized parallel processing for matrix operations.
• Programmability: Fully programmable via a dedicated, streamlined matrix Instruction Set Architecture (ISA) extension for RISC-V.
• Technology Node: Evaluation metrics (PPA) were derived from post-synthesis results using a mature 65-nm technology node.
• Area Metrics: The coprocessor requires only 0.65 mm² of silicon area.

Implications

• Driving Edge AI: Quadrilatero provides a highly optimized solution for deploying complex AI models requiring intensive matrix multiplications directly on low-power edge devices, facilitating the rapid growth of distributed AI in IoT.
• RISC-V Ecosystem Expansion: By proposing and implementing a streamlined matrix ISA extension, this work contributes to the potential standardization and adoption of efficient matrix acceleration extensions within the open-source RISC-V domain.
• Addressing Vector Bottlenecks: It validates a paradigm shift away from purely vector-based processing for pervasive AI workloads, demonstrating that dedicated matrix acceleration architectures (systolic arrays) are superior in terms of power and area efficiency for MatMul operations.