Abstract

This paper addresses the prevention of microarchitectural covert channels that exploit shared hardware resources to leak information across OS security boundaries, focusing on the open-source 64-bit RISC-V Ariane core. Initial attempts using software-only time protection mechanisms in the seL4 microkernel proved expensive and incomplete against five evaluated channels. The key innovation is the addition of a single-instruction RISC-V ISA extension designed to flush microarchitectural state, which closes all evaluated covert channels efficiently and with minimal overhead.

Report

Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core

Key Highlights

• Problem Addressed: Information leakage via microarchitectural covert channels, which exploit timing variations resulting from competition for limited hardware resources.
• Target System: Evaluation was performed on Ariane, an open-source 64-bit application-class RISC-V core.
• Defenses Tested: The efficacy of experimental time protection support within the seL4 microkernel was assessed against five known covert channels.
• Finding: Software-only defenses were confirmed to be both costly and incomplete in mitigating these channels without dedicated hardware support.
• Solution: Introduction of a single-instruction extension to the RISC-V ISA specifically designed to flush microarchitectural state.
• Outcome: This hardware support enables the operating system to successfully close all five evaluated covert channels with minimal impact on performance.

Technical Details

• Architecture Tested: Ariane (64-bit, application-class RISC-V core).
• Security Context: Utilizes the seL4 microkernel's experimental support for time protection.
• Vulnerability Type: Microarchitectural covert channels (timing attacks) that leverage shared resources (e.g., caches, buffers).
• Proposed Mechanism: A new, single instruction added to the RISC-V ISA.
• Functionality: The instruction flushes volatile microarchitectural state, effectively sanitizing the shared resources during security domain transitions (context switches).
• Performance Impact: The proposed mechanism resulted in a low increase in context switch costs and negligible additional hardware overhead.

Implications

• RISC-V Security Baseline: This research demonstrates that purely software-based security mechanisms are insufficient for robustly preventing complex microarchitectural timing attacks on modern RISC-V architectures.
• ISA Extension Necessity: It strongly argues that a hardware mechanism, packaged as an ISA extension for state flushing, is essential for achieving high security guarantees (e.g., COTS evaluation criteria) on RISC-V implementations.
• Ecosystem Development: The successful implementation on Ariane provides a blueprint for security-critical RISC-V implementations, pushing for the standardization or widespread adoption of similar security-focused microarchitectural control instructions across the open-source hardware community.
• Microkernel Validation: Validates the seL4 kernel's efforts in time protection while highlighting the need for underlying processor support to make those efforts effective and practical.