Abstract

This paper presents the design and integration of a Pipelined Full Posit Processing Unit (FPPU) into the low-power Ibex RISC-V core, leveraging the modular RISC-V ISA to enable customized posit arithmetic instructions. The FPPU implements the full suite of arithmetic operations and conversions, offering improved numerical accuracy and range compared to standard floating-point. The integration results in a limited area increase (7% for 8-bit and 15% for 16-bit posits) while demonstrating minimal accuracy loss in deep neural network applications when using 16-bit posits instead of 32-bit IEEE floats.

Report

PPU: Design and Implementation of a Pipelined Full Posit Processing Unit

Key Highlights

• Novel Hardware Unit: Design and implementation of the Full Posit Processing Unit (FPPU) for posit arithmetic.
• Integration Target: Successfully integrated the FPPU into the low-power Ibex RISC-V core through instruction set customization.
• Efficiency Metric: The integration results in minimal area overhead: 7% increase for 8-bit posits and 15% increase for 16-bit posits on the full RISC-V core.
• Numerical Advantage: Posit arithmetic is utilized for its improved numerical accuracy, well-defined behavior, and increased range of representable numbers.
• Application Success: Tests on deep neural networks (DNNs) demonstrated a minimal drop in accuracy when moving from 32-bit IEEE floats to 16-bit posits.

Technical Details

• Unit Name: Full Posit Processing Unit (FPPU).
• Core Architecture: Integrated into the low-power Ibex RISC-V core.
• Supported Operations (Full Posit): Hardware implementation of addition, subtraction, multiplication, division, fused multiply-add (FMA), inversion, float-to-posit conversion, and posit-to-float conversion.
• ISA Methodology: Customization of the RISC-V ISA was used to add posit-specific instructions, utilizing RISC-V's modularity.
• Prototyping: The FPPU was prototyped and evaluated on Alveo and Kintex FPGAs.
• Bit Widths Evaluated: The impact was specifically evaluated for 8-bit and 16-bit posit configurations.

Implications

• RISC-V Extensibility: This work validates the power and flexibility of the open-source RISC-V ISA, demonstrating its utility for integrating non-standard, domain-specific arithmetic units without incurring licensing or royalty fees.
• Low-Power High Accuracy Computing: The FPPU enables low-power cores like Ibex to handle complex real-number processing with higher numerical fidelity than equivalent small floating-point formats, crucial for embedded AI and signal processing applications.
• AI Hardware Acceleration: Showing that 16-bit posits maintain high accuracy in DNNs relative to 32-bit floats provides a strong argument for adopting posits in specialized AI accelerators to significantly reduce power consumption and memory bandwidth requirements without compromising performance.