PERI: A Posit Enabled RISC-V Core

Abstract

This paper introduces PERI, the first Posit Enabled RISC-V core, which integrates the advanced Posit arithmetic format—a superior alternative to IEEE 754—into the extensible RISC-V ISA. The implementation leverages the existing RISC-V 'F' extension and custom op-code space to incorporate a parameterized Floating Point Unit (FPU) into the SHAKTI C-class core. The resulting design supports run-time switching between exponent sizes to optimize for either accuracy or dynamic range, achieving a 100 MHz operating frequency on an Artix-7 FPGA.

Report

Key Highlights

• Novel Integration: PERI is proposed as the first Posit Enabled RISC-V core, merging the highly extensible RISC-V ISA with the Posit numerical format.
• Posit Benefits: Posit is used as a replacement for IEEE 754-2008, promising higher accuracy, greater dynamic range, fewer unused states, and simpler hardware design.
• Base Core: The Posit FPU is integrated with the RISC-V compliant SHAKTI C-class core.
• FPU Flexibility: The FPU supports dynamic switching between two different exponent sizes (while maintaining a 32-bit posit size) to adjust between high-accuracy and high-dynamic-range computation modes at run-time.
• Toolchain Workaround: The paper provides a minimal application modification strategy to utilize the existing RISC-V tool-chain, mitigating the current lack of a viable Posit software tool-chain.

Technical Details

• Arithmetic Format: Posit (introduced mid-2017).
• RISC-V Implementation Strategy: Posit arithmetic is supported by leveraging or modifying the current 'F' extension and utilizing the custom op-code space of the RISC-V ISA.
• Integration Method: The parameterized Posit FPU can be integrated into the SHAKTI C-class core either as a standard execution unit or as a dedicated accelerator.
• Hardware Resource Utilization (Artix-7-100T Xilinx FPGA):
  • Slice LUTs: 3507
  • Slice Registers: 1294
  • Maximum Operating Frequency: 100 MHz
• Numerical Feature: The design specifically enhances the 32-bit Posit FPU to support variable exponent sizes with minimal overheads.

Implications

• Validation of RISC-V Extensibility: This work demonstrates the practical utility and flexibility of the RISC-V ISA, proving its capability to seamlessly adopt radical architectural changes like replacing standard floating-point units with novel arithmetic systems (Posit).
• Future of Numerical Computing: By coupling Posit’s promise of numerical superiority (accuracy, simplicity) with an efficient, open-source core, PERI accelerates the transition toward post-IEEE 754 standards, potentially benefiting applications in machine learning, scientific computing, and embedded systems.
• Hardware Reference for Posit: PERI provides a concrete, synthesized hardware reference for Posit arithmetic, crucial for driving adoption and future software toolchain development within the open-source hardware community.
• Addressing Architectural Constraints: The project directly responds to the challenges posed by the failure of Dennard's scaling by exploring high-efficiency, specialized arithmetic architectures.