PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT Processors

Abstract

PELS (Peripheral Event Linking System) is proposed as a lightweight, flexible solution to manage peripheral interactions in ultra-low-power IoT processors without requiring continuous mediation by the main CPU. This open-source, peripheral-agnostic architecture combines dedicated event routing with a tiny I/O processor to balance efficiency and flexibility. PELS reduces the power consumption of a linking event by 2.5 times compared to a baseline approach, while maintaining a minimal silicon area of just 7 kGE in its smallest configuration.

Report

PELS: A Lightweight and Flexible Peripheral Event Linking System

Key Highlights

• Core Innovation: PELS addresses the challenge of peripheral linking in ultra-low-power (ULP) devices, aiming to reduce the power wasted when the main CPU wakes up simply to mediate peripheral events.
• Hybrid Architecture: The system solves the traditional trade-off between efficient single-wire interconnects and flexible general-purpose I/O processors by combining both: dedicated event routing and a tiny I/O processor.
• Efficiency Gain: PELS achieves a significant power reduction, cutting the power consumption for a linking event by 2.5 times compared to relying on the main core for the linking process.
• Open Source & Agnostic: The system is developed as an open-source, peripheral-agnostic solution, promoting wider integration.

Technical Details

• System Name: Peripheral Event Linking System (PELS).
• Architectural Components: Dedicated event interconnects (routing single-wire event lines) and a specialized, tiny I/O processor.
• Target Application: Ultra-Low Power (ULP) IoT Processors, specifically demonstrated integrated into a ULP RISC-V IoT processor.
• Area Footprint: Low area overhead, measured at just 7 kGE (kilo Gate Equivalents) in its minimal configuration.
• Performance: Power reduction factor of 2.5x for event linking compared to the main CPU baseline.

Implications

• Enhanced ULP Efficiency: By offloading simple peripheral event mediation from the main CPU, PELS allows the core to remain in deeper sleep states longer, significantly extending the battery life of IoT devices.
• Flexibility and Scalability: The hybrid design addresses the need for both high-speed, predictable event handling (via routing) and complex, programmable logic (via the tiny I/O processor), offering superior flexibility over current single-solution approaches.
• RISC-V Ecosystem Advancement: The successful integration of PELS into a ULP RISC-V processor demonstrates a critical architectural improvement for energy efficiency, furthering the RISC-V architecture's competitiveness in the rapidly growing low-power edge and IoT markets.
• Community Adoption: PELS being open-source means hardware designers and silicon manufacturers can readily adopt and customize this lightweight solution, accelerating the development of next-generation power-optimized chips.