Optimizing Energy Efficiency in Subthreshold RISC-V Cores

Abstract

This study analyzes the energy efficiency of six open-source RISC-V cores operating in the subthreshold regime, utilizing a custom library targeting 300 mV in a 130 nm process. The core finding demonstrates that limited-depth pipelined architectures, specifically the 2-stage Vex (Vex-2), achieve the optimal balance between performance and power consumption. Researchers conclude that deeper pipelines yield diminishing performance returns in this ultra-low-voltage domain due to the necessity of adding buffers that increase area and power usage.

Report

Key Highlights

• Primary Goal: To determine how to maximize energy efficiency when designing standard Instruction Set Architecture (ISA) processor cores specifically for subthreshold operation.
• Sweet Spot Identified: Limited-depth pipelined RISC-V designs (like Vex-2) represent the "sweet spot" for energy efficiency, offering high performance relative to their power consumption in the subthreshold domain.
• Vex-2 Performance: The 2-stage Vex (Vex-2) was identified as the most energy-efficient core overall.
• Deep Pipelining Challenge: Deeper pipelines (e.g., Vex-5 and Rocket) suffer from diminished returns in subthreshold operation because longer wires necessitate the addition of buffers to maintain a competitive cycle time. These buffers subsequently increase power consumption and area.
• Pareto Optimal Cores: SERV, QERV, PicoRV32, and Vex were found to be Pareto optimal across performance, power, and area metrics.

Technical Details

• Operating Regime: Subthreshold operation (ultra-low voltage).
• Target Specs: 300 mV supply voltage in a commercial 130 nm fabrication process.
• Library: A custom subthreshold library was developed and used for synthesizing the cores.
• Cores Tested (Multi-Cycle): SERV, QERV, and PicoRV32.
• Cores Tested (Pipelined): Ibex, Rocket, and two variants of Vex (Vex-2 and Vex-5).
• Performance Limiter: For pipelined architectures in subthreshold, cycle time scaling is limited by the need to buffer signals across longer wires. This buffering prevents the performance gains from scaling proportionally with the number of pipeline stages, resulting in cores like Vex-2 achieving similar performance but lower power consumption than 5-stage designs.

Implications

• RISC-V Optimization Guidance: This work provides critical architectural guidelines for the RISC-V ecosystem, suggesting that highly specialized, simplified pipelines (2-stage) are superior to complex, deep pipelines when the primary design constraint is maximizing energy efficiency (Energy Per Instruction).
• IoT and Ultra-Low Power Devices: The findings are directly relevant for designing battery-operated Internet of Things (IoT) devices, biomedical sensors, and other edge computing hardware where operation must be sustained for long periods on minimal energy.
• Architectural Trade-offs Redefined: It highlights that traditional performance optimization techniques (deeper pipelining) fail in the ultra-low-voltage regime, forcing architects to prioritize reduced area and simpler logic to maintain low power consumption while benefiting from minimal pipelining effects.