On the Simulation of Hypervisor Instructions for Accurate Timing Simulation of Virtualized Systems

Abstract

Traditional full-system simulators for virtualized environments often abstract hypercalls, causing inaccurate timing results. This paper introduces a novel simulation approach that explicitly executes hypervisor instructions alongside OS and application code. This methodology, demonstrated via a Verilog-coded, functional-first simulator for RISC-V binaries, achieves significantly more accurate timing simulation for virtualized systems.

Report

Key Highlights

• Problem Addressed: Existing full-system simulators suffer from timing inaccuracy because they abstract the execution path of hypercalls (traps to the hypervisor).
• Core Innovation: The proposed approach simulates the complete instruction set, including application, operating system, and hypervisor instructions, to capture the true latency of virtualization events.
• Validation Target: The proposed method is demonstrated using RISC-V binary instructions.
• Result: The explicit simulation of hypervisor instructions successfully leads to accurate timing simulation of virtualized systems.

Technical Details

• Simulator Type: The implementation is described as an execution-driven simulator.
• Design Paradigm: It follows a "functional-first" approach, suggesting robust functional correctness precedes detailed timing analysis.
• Implementation Stack: The simulator is characterized as "hardware-based" and is coded using the hardware description language, Verilog.
• Simulation Scope: It covers the full virtualization stack, executing RISC-V binary instructions across different privilege levels (application, OS, and hypervisor).

Implications

• Advancing RISC-V Virtualization: Since the demonstration uses RISC-V binaries, this tool is vital for accurately modeling the performance impact of the RISC-V H-extension (Hypervisor extension) and evaluating its efficiency.
• Accurate Architecture Exploration: Provides computer architects designing new hardware features the precise timing data needed to understand the overhead introduced by virtualization management, ensuring better architectural design choices.
• Reliable Performance Prediction: Enables far more reliable performance modeling for complex virtualized workloads running on RISC-V systems, which is critical for datacenter and edge computing applications relying on virtualization technology.
• Tooling Improvement: Addresses a recognized limitation in existing simulation tools, making next-generation architectural simulators more useful and trustworthy for evaluating modern software stacks.