MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference

Abstract

MultiVic is a novel, time-predictable RISC-V multi-core vector processor designed to meet the high-performance and strict predictability requirements of neural network inference in real-time systems. The architecture ensures predictable timing behavior by using a central management core to orchestrate shared memory access based on a statically determined schedule, thereby avoiding memory interference. Evaluation shows that configurations with more, smaller cores maximize performance due to increased effective memory bandwidth and higher clock frequencies, all while maintaining minimal execution time fluctuation.

Report

Key Highlights

• Target Domain: Solves the challenge of integrating high-performance neural networks (NN) into safety-critical, real-time systems (e.g., automated driving).
• Core Innovation: Introduces MultiVic, a multi-core RISC-V vector processor architecture specifically designed for time predictability.
• Predictability Mechanism: Achieves predictability by eliminating memory interference through a central management core that controls access to shared external memory via a statically determined schedule.
• Performance Finding: Performance is optimized using configurations with a larger number of smaller cores, which enhance effective memory bandwidth and clock frequencies.
• Crucial Result: Execution time fluctuation remains very low across different configurations, confirming the platform’s real-time capability.

Technical Details

• Architecture: Multi-core vector processor.
• Core Design: Individual cores are designed to be predictable and are equipped with their own local scratchpad memories.
• Memory Hierarchy: A two-tier structure where local scratchpads provide fast access, and a central management core governs the predictable flow to shared external memory.
• Scheduling Method: External memory access is managed strictly using a statically determined schedule to prevent concurrent resource contention (memory interference).
• Parametric Evaluation: The design was analyzed across variants, comparing the multi-core setup against a baseline architecture consisting of a single-core vector processor with large vector registers.

Implications

• Advancing Real-Time AI: MultiVic offers a crucial architectural blueprint for bridging the existing gap between high-performance AI accelerators (which are often unpredictable) and traditional real-time hardware (which often lacks sufficient compute resources).
• RISC-V Ecosystem Relevance: Demonstrates the flexibility and capability of the RISC-V ISA for creating highly specialized, time-predictable Domain-Specific Architectures (DSAs) required for critical embedded applications.
• Safety-Critical Systems: By guaranteeing low execution time fluctuation, this architecture enables the safe deployment of complex, state-of-the-art neural networks in environments where deterministic timing is paramount.
• Design Optimization: The finding that smaller, numerous cores are superior to fewer, larger cores informs future design decisions for maximizing parallel performance under strict timing constraints.