Multi-Dimensional Vector ISA Extension for Mobile In-Cache Computing

Abstract

This paper introduces the Multi-dimensional Vector ISA Extension (MVE) designed specifically for mobile In-Cache Computing (ICC), addressing the inefficiency of existing 1D vector ISAs like RVV when utilizing wide SIMD units. MVE enables multi-dimensional memory accesses and dimension-level masked execution, abstracting cache geometry for flexible programming. This approach yields substantial efficiency gains, showing 2.9x performance improvement and 8.8x energy reduction on average compared to commercial mobile processors, with only 3.6% area overhead.

Report

Multi-Dimensional Vector ISA Extension for Mobile In-Cache Computing

Key Highlights

• Innovation: Introduction of the Multi-dimensional Vector ISA Extension (MVE) to optimize performance for "in-cache computing" technology in mobile CPUs.
• Problem Solved: Existing long-vector ISAs (like RVV and Arm SVE) are limited to one-dimensional access, which poorly utilizes the large SIMD widths available in in-cache vector engines due to limited parallelism in mobile data-parallel kernels.
• Performance Metrics: MVE delivers a 2.9x average performance increase and an 8.8x average energy reduction compared to the SIMD units of a commercial mobile processor.
• Cost Efficiency: The implementation requires a minimal 3.6% area overhead.

Technical Details

• Target Application: Mobile vector kernels and data-parallel workloads running on mobile CPUs.
• Core Concept (ICC): In-cache computing transforms existing caches into long-vector compute units, offering a low-cost alternative to building expensive vector engines.
• MVE Features: The proposed ISA extension specifically addresses limitations in memory access and execution masking:
  • Multi-dimensional strided memory accesses.
  • Multi-dimensional random memory accesses.
  • Efficient dimension-level masked execution.
• Design Goal: MVE is engineered to abstract cache geometry and data layout, enabling parallelism to be encoded across multiple dimensions, thereby ensuring high utilization of wide SIMD resources.

Implications

• Mobile Computing Efficiency: MVE provides a critical architectural pathway for achieving high performance and substantial energy savings in power-constrained mobile devices by maximizing the compute potential of existing cache structures.
• RISC-V/ISA Ecosystem Relevance: The paper strongly suggests that existing standardized vector extensions (like RVV) are insufficient for modern, wide-SIMD, specialized architectures like ICC. This necessitates the adoption of multi-dimensional memory access features for optimal performance in these domains.
• Hardware Design: The low area overhead (3.6%) combined with massive performance/energy gains validates MVE as an extremely efficient and practical architectural modification for improving mobile processor capabilities.