Monte Cimone: Paving the Road for the First Generation of RISC-V High-Performance Computers

Abstract

Monte Cimone is a fully-operational, multi-blade computer prototype designed as a hardware-software test-bed to explore the challenges of integrating RISC-V into High-Performance Computing (HPC) environments. Utilizing the 64-bit U740 multi-core SoC, the project focused on achieving holistic co-design across memory, storage, interconnects, and the full software stack. The success of this integration demonstrates a remarkable level of maturity, suggesting that the first generation of production RISC-V HPC machines is rapidly approaching realization.

Report

Monte Cimone: Analysis Report

Key Highlights

• RISC-V HPC Prototype: Monte Cimone is a multi-blade computer prototype built specifically to address the challenges of creating multi-node RISC-V clusters for High-Performance Computing (HPC).
• Holistic Co-Design Focus: The primary goal was not achieving peak floating-point performance, but rather “priming the pipe” by exploring the entire hardware-software co-design effort required for HPC.
• Operational Test-Bed: The prototype is described as fully-operational and serves as a complete hardware-software test-bed.
• Integration Success: The project successfully integrated a complete HPC production stack, including interconnect, storage, and power monitoring infrastructure.
• Maturity Indication: The results demonstrate high levels of software and hardware readiness, suggesting the rapid feasibility of first-generation RISC-V HPC systems.

Technical Details

• Architecture Base: The system is built upon a multi-blade computer configuration.
• Central Processor: The prototype utilizes the U740, a 64-bit RISC-V System-on-Chip (SoC).
• Computational Capability: The U740 SoC used is specifically noted as being double-precision capable.
• Tested Components: The integration effort covered all elements necessary for a production cluster environment, including: memory hierarchy, storage, high-speed interconnects, and comprehensive power monitoring infrastructure.

Implications

• Validation of RISC-V for HPC: Monte Cimone provides crucial evidence that RISC-V is viable beyond microcontrollers and embedded systems, positioning it as a serious contender in the high-performance computing market.
• Accelerated Ecosystem Development: By identifying and solving integration challenges—particularly around networking and storage needed for multi-node clustering—the project accelerates the development and maturation of the RISC-V HPC software stack.
• Reference Architecture: The operational prototype serves as a vital blueprint and reference architecture for future commercial or academic ventures seeking to build scalable RISC-V supercomputers.
• Open Hardware Momentum: The successful creation of a complex, multi-node system reinforces the benefits of the open and royalty-free RISC-V Instruction Set Architecture (ISA) for cutting-edge computing initiatives.