Mixed-Level Modeling and Evaluation of a Cache-less Grid of Processing Cells

Abstract

This article introduces a novel architecture based on a cache-less grid composed of numerous processing cells, designed to maximize parallelism and efficiency for embedded applications. The core innovation lies in utilizing a mixed-level modeling methodology, which allows for robust and accurate performance evaluation across different abstraction levels. This evaluation framework is critical for validating the unique distributed memory access strategies required by cache-less systems and optimizing the overall design space.

Report

Key Highlights

• Novel Architecture: Focuses on a specialized "Cache-less Grid of Processing Cells" designed for high-throughput, parallel computation, often targeting domain-specific or streaming applications.
• Mixed-Level Modeling: The primary contribution is the methodology, which combines high-speed architectural models (like Transaction-Level Modeling) with detailed, cycle-accurate models (like RTL) to enable rapid yet precise design space exploration.
• Cache-less Paradigm: Addresses the challenges of memory management and communication overhead inherent in architectures that eschew traditional hardware caches, relying instead on explicit or distributed memory structures (e.g., Scratchpad Memories).
• Evaluation Focus: Aims to rigorously evaluate the performance and efficiency of the grid, specifically targeting metrics relevant to many-core embedded systems such as latency, power consumption, and area efficiency.

Technical Details

• Architecture Type: Assumed to be a Near-Threshold Computing or Many-Core Accelerator topology, where processing elements (PEs) are arranged in a regular grid or mesh.
• Memory Strategy: Cache-less design dictates the use of highly localized, software-managed memories (Scratchpad Memories) and explicit data movement via DMA controllers or dedicated network-on-chip (NoC) messaging.
• Modeling Stack: The "mixed-level" methodology likely integrates models written in multiple languages (e.g., C++/SystemC for TLM; VHDL/Verilog for RTL) to provide a performance bridge between early architectural analysis and physical implementation constraints.
• Evaluation Criteria: Evaluation would typically include benchmarking with representative parallel workloads (e.g., signal processing, matrix operations) to measure speedup and scalability under the constraint of explicit memory synchronization.

Implications

• RISC-V Customization: The RISC-V ecosystem strongly encourages architectural specialization. A cache-less grid architecture is perfectly suited for integrating tailored, minimal RISC-V cores as the Processing Cells, optimizing them strictly for area and power efficiency rather than complex general-purpose pipelines.
• Verification Methodology Advancement: The successful deployment of a mixed-level modeling methodology provides a critical blueprint for other RISC-V designers working on highly integrated SoCs and accelerators, allowing them to verify complex memory hierarchies and NoC interactions much earlier in the design flow.
• Embedded and Edge AI: Cache-less architectures are crucial for memory-bound tasks common in Edge AI and embedded machine learning, where predictable, low-latency memory access (rather than highly optimized average-case performance) is paramount. This work advances the foundation for specialized RISC-V hardware in these domains.
• Pioneering Many-Core Research: This architecture pushes the boundaries of efficient, explicit parallel processing, offering alternatives to traditional shared-memory CMPs (Chip Multiprocessors) that often suffer from cache coherence overheads.