MEDEA: A Design-Time Multi-Objective Manager for Energy-Efficient DNN Inference on Heterogeneous Ultra-Low Power Platforms

MEDEA: A Design-Time Multi-Objective Manager for Energy-Efficient DNN Inference on Heterogeneous Ultra-Low Power Platforms

Abstract

MEDEA is a novel design-time multi-objective manager focused on maximizing energy efficiency for Deep Neural Network (DNN) inference on Heterogeneous Ultra-Low Power (HULP) platforms. It integrates kernel-level Dynamic Voltage and Frequency Scaling (DVFS), adaptive tiling, and fine-grained scheduling to minimize energy while strictly adhering to application deadlines and memory constraints. Evaluated on a RISC-V based heterogeneous platform, MEDEA achieves energy reductions of up to 38% compared to existing methods, confirming its effectiveness for critical edge AI applications.

Report

Key Highlights

  • Innovation: Introduction of MEDEA, a design-time multi-objective manager specifically for energy-efficient DNN inference on Heterogeneous Ultra-Low Power (ULP) platforms.
  • Primary Goal: Minimizing execution energy while simultaneously meeting strict application timing deadlines and memory footprint constraints.
  • Performance Gain: Demonstrated energy reductions of up to 38% compared to representative state-of-the-art optimization methods.
  • Critical Feature Impact: Analysis showed that kernel-level DVFS alone can be responsible for over 31% of the observed energy savings in specific operational scenarios.
  • Validation: Successfully validated using a real-world biomedical case study: seizure detection.

Technical Details

  • Optimization Strategy: Design-time optimization based on timing constraints to achieve minimum energy consumption.
  • Target Architecture: Heterogeneous Ultra-Low Power (HULP) platforms.
  • Evaluation Platform: The HEEPtimize platform, implemented in a 22 nm process and FPGA-prototyped.
  • Processing Elements (PEs): The HEEPtimize platform incorporates a diverse set of PEs, including a standard RISC-V processor and specialized accelerators like Near-Memory Computing (NMC) and Coarse-Grained Reconfigurable Array (CGRA).
  • Core MEDEA Methods:
    • Kernel-level DVFS: Dynamic energy adaptation applied at the granularity of individual DNN kernels.
    • Kernel-level Granularity Scheduling: Fine-grained resource assignment suitable for specialized accelerator management.
    • Memory-Aware Adaptive Tiling: Strategy designed to handle severe memory constraints characteristic of ULP systems.

Implications

  • Enabling Ultra-Low Power Edge AI: MEDEA addresses a crucial challenge in edge computing: deploying complex, computationally demanding DNNs onto severely resource-constrained devices (ULP platforms) without sacrificing energy efficiency or reliability.
  • RISC-V Ecosystem Relevance: The successful integration and management of the heterogeneous HEEPtimize platform, anchored by a RISC-V core coordinating specialized accelerators (NMC, CGRA), validates RISC-V's role as the indispensable control processor for next-generation AI-optimized SoCs.
  • Heterogeneous Management Solution: Provides a necessary blueprint for managing architectural complexity. As chips rely increasingly on specialized accelerators for performance, design-time managers like MEDEA are essential for effectively leveraging features like fine-grained DVFS and scheduling to unlock maximal energy savings across disparate processing elements.
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