Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing

Abstract

Lyra is a novel heterogeneous RISC-V verification framework that pairs hardware acceleration via an FPGA SoC with an ISA-aware generative model, LyraGen, for processor fuzzing. This methodology enables high-throughput differential checking and generation of semantically rich test stimuli, addressing the limitations of slow software simulation and low-quality random tests. Lyra achieves up to 1.27x higher coverage and dramatically accelerates end-to-end verification by up to 3343x compared to state-of-the-art software fuzzers.

Report

Key Highlights

• Novel Framework: Lyra is introduced as a heterogeneous RISC-V verification framework designed to overcome verification bottlenecks.
• Dual Innovation: It combines hardware acceleration (using an FPGA SoC) for speed with a generative model (LyraGen) for high-quality, semantically rich stimuli generation.
• Performance Leap: The framework accelerates end-to-end verification throughput by a factor ranging from $107\times$ up to $3343\times$ when compared against existing state-of-the-art software fuzzers.
• Coverage Improvement: Lyra consistently achieves up to $1.27\times$ higher coverage and demonstrates lower convergence difficulty.

Technical Details

• Architecture: Lyra utilizes an FPGA System-on-Chip (SoC) to execute both the Device Under Test (DUT) and a corresponding reference model concurrently.
• Verification Methodology: Verification is based on high-throughput differential checking, leveraging the parallelism and speed afforded by the hardware acceleration.
• Fuzzing Model (LyraGen): Instead of relying on semantically blind random mutations, Lyra employs a domain-specialized, ISA-aware generative model (LyraGen). This model is trained to produce instruction sequences with inherent semantic richness, improving test quality.
• Data Collection: The hardware platform facilitates efficient collection of hardware-level coverage metrics.

Implications

• Addressing Verification Bottlenecks: Lyra directly tackles the critical challenge of slow software simulation and inadequate test stimuli quality, which currently bottlenecks processor development.
• Enhancing RISC-V Reliability: By accelerating verification and achieving deeper coverage via semantically aware testing, Lyra enables faster and more reliable development cycles for complex RISC-V core designs.
• Reducing Verification Costs: The massive acceleration factors (up to $3343\times$) can significantly lower the time and computational resources required for thorough processor verification, making advanced verification more accessible and cost-effective.
• Advancing AI in Hardware Verification: The use of a specialized generative model (LyraGen) demonstrates a successful path forward for integrating sophisticated machine learning techniques into the hardware design and verification flow.