LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems through Polling-Free and Retry-Free Operation

Abstract

The LRSCwait paper introduces LRwait and SCwait, a novel synchronization pair designed to eliminate performance-degrading polling and retries common in traditional Load-Reserved/Store-Conditional (LRSC) operations on manycore systems. The proposed Colibri architecture scalably manages these primitives by allowing contending cores to sleep, ensuring polling-free and retry-free operation. Benchmarked on a 256-core RISC-V platform, Colibri achieves a 6.5x throughput improvement and 7.1x greater energy efficiency over LRSC-based methods with only 6% area overhead.

Report

Key Highlights

• Core Innovation: Introduces the LRwait and SCwait synchronization primitives to enable polling-free and retry-free atomic operations.
• Problem Solved: Eliminates extensive polling in shared-memory manycore systems, which typically causes contention, low throughput, and poor energy efficiency in standard LRSC and lock implementations.
• Scalable Implementation: The innovation is realized through Colibri, a distributed and scalable architecture responsible for managing LRwait reservations.
• Performance Metrics: Colibri achieves a 6.5x speedup in throughput and a 7.1x improvement in energy efficiency compared to traditional LRSC implementations.
• Overhead: The necessary hardware modifications incur a minimal area overhead of only 6%.
• Validation Platform: Extensive benchmarking was performed on an open-source RISC-V platform featuring 256 cores.

Technical Details

• Primitive Function: LRwait and SCwait operate as a synchronization pair. Unlike conventional LRSC where waiting cores actively poll (spin), cores attempting LRwait enter a sleep state while awaiting access completion by the prior core.
• Colibri Architecture: This architecture manages the coordination of sleeping cores and reservations in a distributed manner, which is crucial for maintaining scalability as core count increases.
• Comparison Baseline: The solution directly targets the inefficiencies found in generalized atomic operations like Load-Reserved/Store-Conditional (LRSC), which inherently cause serialization and retries leading to performance degradation under high contention.
• Test Environment: The implementation was tested on a large-scale RISC-V system, specifically an open-source platform designed to handle 256 cores, validating its effectiveness in massive manycore environments.

Implications

• Enhanced Manycore Scalability: LRSCwait addresses a fundamental bottleneck in synchronization, making it practical to scale shared-memory architectures beyond current limitations without suffering major performance penalties from communication overhead.
• RISC-V Ecosystem Advancement: By being validated on an open-source RISC-V platform, this work offers a critical, high-performance synchronization primitive that can be readily adopted by high-core-count RISC-V processor designs (e.g., in HPC or data center accelerators).
• Energy Efficiency in HPC: The 7.1x gain in energy efficiency is profoundly important for power-constrained environments, providing a crucial improvement for sustainable high-performance computing.
• Atomic Operation Evolution: This proposal suggests a necessary evolution for atomic instruction sets, moving away from simple polling mechanisms towards sophisticated, hardware-managed sleep/wake synchronization protocols.