Lifetime-Aware Design of Item-Level Intelligence

Abstract

We present FlexiFlow, a lifetime-aware design framework utilizing natively flexible electronics and area-optimized RISC-V cores for Item-Level Intelligence (ILI) embedded in disposable products. The framework addresses the 1000X operational lifetime variability in ILI applications by modeling and optimizing the trade-offs between embodied and operational carbon footprints. This holistic, sustainability-driven approach, validated via the first open-source tape-out on flexible electronics, demonstrated carbon footprint reductions up to 14.5X.

Report

Structured Report: Lifetime-Aware Design of Item-Level Intelligence

Key Highlights

• FlexiFlow Framework: A design framework optimizing Item-Level Intelligence (ILI)—computation integrated into disposable products (e.g., packaging, medical patches).
• Target Technology: Natively flexible electronics, characterized by low cost but severe resource constraints (kHz speeds, limited to thousands of gates).
• Lifetime Variability: The core innovation is accounting for the 1000X variation in operational lifetime observed across ILI applications, which fundamentally changes optimal architectural design choices at trillion-item deployment scales.
• Sustainability Focus: The design process is driven by a carbon-aware model that balances the embodied carbon (manufacturing footprint) and operational carbon (usage footprint).
• Significant Gains: The framework achieves substantial sustainability improvements, reducing carbon footprint by 1.62X (microarchitecturally) and up to 14.5X (algorithmically).

Technical Details

• Architectural Components: FlexiFlow includes three main elements:
  1. FlexiBench: A workload suite specifically designed for sustainability applications, ranging from food spoilage detection to health monitoring.
  2. FlexiBits: Highly area-optimized RISC-V cores featuring extremely narrow 1-bit, 4-bit, and 8-bit datapaths.
  3. Carbon-Aware Model: A holistic model used to select the optimal architecture based on the specific deployment characteristics and application lifetime requirements.
• Efficiency: FlexiBits cores achieve 2.65X to 3.50X better energy efficiency per workload execution compared to conventional designs.
• Validation and Open Source: The approach was validated through a successful tape-out using a flexible electronics Process Design Kit (PDK). This was achieved entirely using fully open-source EDA tools.
• Performance Metrics: The resulting tape-out achieved an operational speed of 30.9kHz, sufficient for the extreme constraints of ILI applications.

Implications

• RISC-V at the Extreme Edge: This work establishes RISC-V as a foundational architecture for the rapidly emerging field of Item-Level Intelligence and “Extreme Edge” computing. By implementing 1-bit and 4-bit cores (FlexiBits), it showcases the unparalleled flexibility and customizability of the RISC-V ISA to meet severe constraints that traditional 32-bit architectures cannot economically or spatially address.
• New Design Paradigm: FlexiFlow introduces application lifetime and resultant carbon footprint as primary metrics for hardware design, moving beyond traditional power, performance, and area (PPA). This shifts the focus toward holistic sustainability for disposable electronics.
• Validation of Open-Source Ecosystem: The successful tape-out using a flexible electronics PDK and fully open-source tools demonstrates the maturity and viability of the open-source hardware ecosystem (crucial for RISC-V adoption) in tackling state-of-the-art, non-traditional fabrication technologies.