Leverage the Average: Averaged Sampling in Pre-Silicon Side-Channel Leakage Assessment

Abstract

This paper introduces Averaged Sampling, a novel technique to significantly reduce the power simulation cost associated with pre-silicon side-channel leakage assessment. By downsampling and averaging high-resolution power traces, the methodology drastically cuts data volume without compromising the quality of leakage detection. Applied to a gate-level RISC-V SoC assessment, this approach demonstrates up to a 6.5-fold improvement in simulation speed.

Report

Key Highlights

• Cost Reduction: The primary goal is reducing the high computational cost of generating necessary high-resolution power traces for pre-silicon side-channel leakage assessment.
• Averaged Sampling: The core innovation is using downsampling and subsequent averaging of high-resolution traces to compress the data.
• Performance Gain: The method achieved an improvement of up to 6.5-fold in power-simulation speed during validation.
• Leakage Quality Maintained: The reduction in simulation effort does not result in a significant loss of side-channel leakage assessment quality.
• Theoretical Basis: The paper provides a theoretical foundation and clarifies the specific conditions under which Averaged Sampling is effective.

Technical Details

• Methodology: Averaged Sampling acts as a data compression technique applied to the simulation output (power traces). It transforms many high-resolution, time-dependent power measurements into a smaller set of averaged data points.
• Assessment Target: The technique was validated on a gate-level implementation.
• Architecture Tested: The reported results utilize a RISC-V System-on-Chip (SoC) for the side-channel leakage assessment demonstration.
• Context: The work was presented at the Proceedings of the Great Lakes Symposium on VLSI 2022 (GLSVLSI '22).

Implications

• Accelerated Security Assessment: By achieving a 6.5x speedup, hardware designers can integrate rigorous security analysis (like side-channel checks) much earlier and more frequently in the development cycle, shifting left the security focus.
• Lower Barrier to Entry: The reduced simulation time and computational resources make side-channel verification more accessible for smaller teams and academic projects, which is critical for the growing, diverse RISC-V ecosystem.
• Enhancing RISC-V Security: Since RISC-V allows custom instruction set extensions and architectural modifications, efficient pre-silicon verification tools are vital for ensuring that new designs do not inadvertently introduce vulnerabilities. Averaged Sampling makes this verification practical.
• Improved Time-to-Market: Faster simulation allows quicker iterations on mitigation techniques (e.g., masking or shuffling), leading to a quicker deployment of secure hardware products.