Late Breaking Results: A RISC-V ISA Extension for Chaining in Scalar Processors

Abstract

Modern accelerators relying on scalar in-order cores often suffer from pipeline stalls, an issue traditionally mitigated by loop unrolling which increases undesirable register pressure. This work introduces 'scalar chaining,' a novel hardware-software solution implemented as a RISC-V ISA extension to eliminate these stalls while maintaining flexibility. Applied specifically to register-limited stencil codes, this extension achieves impressive results, demonstrating >93% FPU utilization, a 4% speedup, and 10% higher energy efficiency over highly-optimized baselines.

Report

Key Highlights

• Target Architecture: Focuses on improving performance in area- and energy-efficient scalar in-order cores (Processing Elements or PEs), commonly used in modern general-purpose accelerators.
• Core Innovation: Proposes "scalar chaining," a hybrid hardware-software solution implemented as a RISC-V Instruction Set Architecture (ISA) extension.
• Problem Solved: Addresses pipeline stalls without the negative side effect of high register pressure, which plagues traditional software optimization methods like loop unrolling.
• Performance Gains: Achieves robust performance metrics, including greater than 93% FPU utilization, a 4% speedup, and a 10% increase in energy efficiency on average.
• Open Source: The implementation is fully open source, ensuring performance experiments are reproducible using free software.

Technical Details

• Mechanism: The solution is termed "scalar chaining," suggesting a data-forwarding or dependency-handling mechanism built directly into the processor pipeline, managed through the new ISA instructions.
• Implementation Base: The chaining is integrated as an extension to the RISC-V ISA.
• Optimization Target: Specifically demonstrated to be effective on register-limited stencil codes, a class of computationally intensive kernels frequently used in accelerators.
• Context: The innovation directly addresses the sensitivity of in-order core pipelines to stalls, maximizing resource usage (FPU).

Implications

• Accelerator Design: This extension enhances the feasibility and efficiency of using simple, low-power scalar in-order cores in accelerators, offering high performance without requiring complex out-of-order execution logic.
• RISC-V Ecosystem Growth: By providing a standardized, open-source ISA extension for chaining, it creates a crucial optimization lever for vendors building RISC-V based PEs and compute fabrics.
• Energy Efficiency: The 10% increase in energy efficiency is highly significant for devices operating under stringent power delivery and thermal dissipation constraints, common in edge computing and HPC.
• Software Flexibility: It allows compiler writers and application developers to mitigate latency stalls effectively, offering better performance than pure software approaches without sacrificing register space for aggressive loop transformations.