Klessydra-T: Designing Vector Coprocessors for Multi-Threaded Edge-Computing Cores

Abstract

Klessydra-T investigates methodologies for designing vector coprocessors tailored for Interleaved-Multi-Threading (IMT) RISC-V cores targeting edge-computing applications. The core goal is to efficiently accelerate computation-intensive kernels, such as AI convolutions and matrix multiplication, crucial for achieving energy efficiency and low hardware cost in edge devices. The study explores architectural alternatives and demonstrates the synergistic effectiveness of combining the intrinsic thread-level parallelism of IMT with data-level parallelism (DLP) provided by vector coprocessing.

Report

Key Highlights

• Target Application: Focuses on computation-intensive kernels (e.g., convolutions, matrix multiplication, Fourier transform) fundamental to edge-computing AI, signal processing, and cryptographic applications.
• Core Architecture: Utilizes Interleaved-Multi-Threading (IMT) processor cores, which are favored for their low hardware cost and energy efficiency in edge environments.
• Key Innovation (Klessydra-T): Proposes and explores alternatives for implementing specialized vector coprocessing units specifically integrated within IMT RISC-V cores.
• Core Finding: The research shows a beneficial synergy between IMT (Thread-Level Parallelism) and Data-Level Parallelism (DLP) when vector coprocessing is applied to target computational workloads.

Technical Details

• Processing Approach: Adopts a vector approach to accelerate data-heavy computations, addressing the limitations of scalar IMT cores when faced with massive data parallelism.
• Platform: The investigation is focused specifically on implementations within the flexible RISC-V Instruction Set Architecture (ISA).
• Design Trade-offs: The study prioritizes design choices that optimize for high throughput on specific kernels while adhering to strict energy efficiency and minimized hardware area requirements characteristic of edge devices.
• Methodology: The paper analyzes various architectural implementations (alternatives) for integrating the vector coprocessor to maximize the concurrent execution benefits derived from both IMT and DLP.

Implications

• Edge AI Acceleration: Klessydra-T offers a viable pathway for running sophisticated machine learning and signal processing algorithms directly on low-power, constrained edge devices without necessitating massive, dedicated ASIC hardware.
• RISC-V Ecosystem Growth: This work expands the design space for RISC-V cores, demonstrating that multi-threading combined with vector extensions (like the proposed coprocessor) can create highly specialized, efficient compute units superior to simple scalar cores for critical application domains.
• Efficiency Model: By leveraging IMT to mask memory latencies and vector units to maximize data throughput, the Klessydra-T design provides an important architectural model for maximizing computational output per watt and per area, crucial metrics for the embedded and IoT sectors.