JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V and SPARC FPGA Soft-cores

Abstract

JuxtaPiton is introduced as the first open-source, general-purpose, heterogeneous-ISA processor designed to enable crucial energy efficiency research. It integrates a small RISC-V core alongside a modified OpenSPARC T1 core within the OpenPiton framework. The system utilizes vital FPGA emulation infrastructure, allowing it to boot full-stack Debian Linux for comprehensive area, timing, and performance analysis.

Report

Key Highlights

• First Open-Source Heterogeneous-ISA Processor: JuxtaPiton is the first publicly available, general-purpose processor combining different Instruction Set Architectures (ISAs) for research purposes.
• Architectural Combination: The platform integrates a small RISC-V core with the modified OpenSPARC T1 core that forms the basis of the OpenPiton framework.
• Research Motivation: Developed to explore the potential for achieving further energy efficiency gains through heterogeneous-ISA microarchitectures, addressing challenges posed by the end of Dennard scaling.
• FPGA Prototyping: Leverages OpenPiton's infrastructure to provide the emulation speed necessary for effective heterogeneous-ISA research via FPGA.
• Full-Stack Capability: The system inherits the ability to boot and run full-stack Debian Linux.

Technical Details

• Project Name: JuxtaPiton.
• Base Framework: OpenPiton (originally developed around OpenSPARC T1).
• Core Integration: A new, small RISC-V core was successfully integrated into the OpenPiton structure.
• ISA Heterogeneity: The system features cores implementing both RISC-V and SPARC ISAs operating within the same chip framework.
• Target Metrics for Investigation: Area effects (on FPGA), timing effects (on FPGA), and performance evaluation using microbenchmarks.

Implications

• Democratization of Research: JuxtaPiton provides the first open-source, general-purpose hardware platform specifically designed for exploring heterogeneous-ISA research, which was previously unavailable.
• Validation of RISC-V Flexibility: The successful integration of the RISC-V core into the complex, established OpenPiton framework demonstrates the flexibility and utility of RISC-V for highly heterogeneous architectures and core mixing.
• Advancing Energy Efficiency: By allowing researchers to investigate how different ISAs and microarchitectures can be optimally paired for specific workloads, this platform directly facilitates the development of more energy-efficient computer architectures.
• Full System Emulation: The ability to boot Debian Linux ensures that research results and architectural innovations tested on JuxtaPiton are relevant to complex, real-world operating environments.