Abstract

Intel has released version 1.29 of its Implicit SPMD Program Compiler (ISPC), marking a significant update that focuses on modernization and architecture expansion. The release notably discontinues support for older Gen9 integrated GPU targets to streamline the codebase and introduces several new performance optimizations. Crucially, ISPC 1.29 also integrates experimental support for the RISC-V architecture, signaling Intel's increasing interest in this emerging ecosystem.

Report

Intel ISPC 1.29 Update Report

Key Highlights

• Experimental RISC-V Support: The most significant addition is the experimental target support for the RISC-V architecture, broadening ISPC's reach beyond traditional Intel platforms.
• Gen9 GPU Targets Dropped: ISPC 1.29 officially removes support for Intel's older Gen9 integrated GPU targets, allowing the codebase to be streamlined and focus resources on newer hardware architectures.
• New Optimizations: The compiler incorporates several new performance optimizations designed to improve code generation and execution efficiency.
• Modernization Focus: The update reflects a broader strategy by Intel to modernize their compiler suite and adapt to evolving hardware landscapes.

Technical Details

• Product: Intel ISPC (Implicit SPMD Program Compiler), a specialized compiler used for high-performance computing, targeting SIMD/vector units effectively.
• Retired Architecture: Gen9 integrated graphics (found in CPUs like Skylake and Kaby Lake) are no longer supported, indicating a move toward Gen10 and newer generations.
• New Architecture: Experimental target support for the RISC-V instruction set architecture (ISA) has been added, leveraging ISPC's ability to efficiently map single-source C/C++ code onto vector units.

Implications

• RISC-V Ecosystem Maturation: Intel's contribution of ISPC—a sophisticated, vectorizing compiler—to the RISC-V ecosystem validates the architecture's growing importance in high-performance computing and specialized acceleration.
• Performance Portability: This addition enables developers to utilize ISPC's specialized vectorization capabilities to write high-performance, parallel code that can be easily ported and optimized for specialized RISC-V implementations.
• Toolchain Expansion: Providing advanced optimization tools like ISPC accelerates the development of efficient software and enhances the overall sophistication of the RISC-V software development toolchain, reducing reliance solely on general-purpose compilers for vectorization.
• Intel Strategy: By supporting RISC-V, Intel demonstrates flexibility and a willingness to participate in non-x86 spaces, potentially positioning ISPC as a cross-platform vectorization solution.