Integrating SystemC-AMS Power Modeling with a RISC-V ISS for Virtual Prototyping of Battery-operated Embedded Devices

Abstract

This paper presents an open-source framework addressing the gap in RISC-V simulation tools by integrating functional instruction set simulation (ISS) with detailed extra-functional power modeling. The framework combines GVSoC for functional RISC-V simulation and SystemC-AMS to model power storage and distribution dynamics. This unified virtual prototyping environment enables accurate Design Space Exploration that captures the critical mutual dependency between system workload and battery life in embedded devices.

Report

Structured Report: Integrating SystemC-AMS Power Modeling with a RISC-V ISS

Key Highlights

• Addresses Simulation Gap: The work tackles the lack of comprehensive simulation frameworks for RISC-V that simultaneously cover functional execution and extra-functional aspects like power consumption.
• Open-Source Framework: The developed solution is provided as an open-source tool to facilitate wide adoption and rapid system-level simulation.
• Unified Simulation Goal: The framework enables Design Space Exploration (DSE) that accurately accounts for the mutual impact between the executed workload (functional) and the power/battery behavior (extra-functional).
• Target Application: The primary focus is on virtual prototyping for compact, battery-powered embedded devices.

Technical Details

• Functional Simulation Component: Functional RISC-V simulation is achieved using GVSoC, an established Instruction Set Simulator (ISS).
• Extra-Functional Modeling Component: Extra-functional aspects, specifically power storage and distribution, are modeled using SystemC-AMS (Analog/Mixed-Signal extensions to SystemC).
• Integration Method: The framework successfully integrates the functional (GVSoC) and extra-functional (SystemC-AMS) models into a single cohesive simulation environment.
• Modeling Scope: The simulation accurately captures how functional events (e.g., instruction execution) influence the power domain (battery depletion) and vice-versa, which is essential for low-power design.

Implications

• Accelerated RISC-V DSE: By providing a fast yet accurate system-level simulation environment, the framework significantly speeds up the Design Space Exploration process for new RISC-V architectures and embedded systems.
• Improved Low-Power Design: The ability to co-simulate instruction execution and realistic battery dynamics allows engineers to optimize power management strategies, duty cycling, and hardware features (like clock gating) with greater confidence before silicon tape-out.
• Ecosystem Maturity: The development of sophisticated, open-source co-simulation tools like this helps mature the overall RISC-V ecosystem, making it a more viable and competitive choice against established proprietary instruction sets, especially in the growing IoT and battery-operated device markets.
• Virtual Prototyping Standard: This work establishes a methodology for high-fidelity virtual prototyping of energy-constrained RISC-V devices, bridging the gap between hardware architecture design and system-level energy analysis.