Increasing the Energy-Efficiency of Wearables Using Low-Precision Posit Arithmetic with PHEE

Abstract

This paper investigates leveraging low-precision posit arithmetic to significantly enhance the energy efficiency of wearable biomedical devices, focusing on applications like ECG analysis and cough detection. The research confirms that low-bit posit formats (as low as 8 bits) can replace standard IEEE 754 floating-point units with minimal accuracy loss. The authors introduce PHEE, a modular RISC-V system integrating the Coprosit posit coprocessor, which achieves up to 54% energy reduction and 38% smaller area compared to a floating-point system on 16nm technology.

Report

Key Highlights

• Energy Efficiency Goal: The primary focus is minimizing battery size and reducing recharging intervals for continuous patient health monitoring devices (wearables).
• Core Innovation: Replacement of traditional IEEE 754 floating-point arithmetic with specialized low-precision posit arithmetic.
• Efficiency Gains: The integrated posit hardware demonstrated up to 54% less energy consumption and was 38% smaller in area compared to a floating-point counterpart, verified via post-synthesis results targeting 16nm TSMC technology.
• Accuracy Maintained: Low-precision posits were validated successfully in key biomedical applications: cough detection and R peak detection in ECG analysis.
• Architectural Framework: The innovation is packaged within PHEE, a modular and extensible architecture built on a RISC-V base, utilizing the dedicated Coprosit posit coprocessor.

Technical Details

• Arithmetic Format: Posit arithmetic (a floating-point-like representation) is used as the high-efficiency alternative to 32-bit IEEE 754 floating-point numbers.
• Bit Precision Results:
  • Cough Detection: 16-bit posits effectively replaced 32-bit IEEE 754 format with minimal accuracy loss.
  • R Peak Detection (ECG): Satisfactory accuracy was achieved using 8-bit or 10-bit posit formats, demonstrating greater bit savings compared to the 16-bit requirement for floating-point formats in this specific task.
• System Architecture (PHEE): PHEE is a modular platform designed for integration into embedded systems. It utilizes the X-HEEP framework (a heterogeneous computing platform) to seamlessly incorporate specialized hardware.
• Hardware Implementation: The posit functionality is delivered via the Coprosit coprocessor, specifically designed to handle posit arithmetic operations and integrated as an accelerator within the RISC-V core system.
• Technology Node: Synthesis results were obtained targeting 16nm TSMC technology.

Implications

• Validation of Posit for Edge Computing: This work provides strong empirical evidence that posit arithmetic is a viable, high-accuracy, and high-efficiency alternative to standard floating-point units for resource-constrained edge devices, especially in the medical IoT field.
• Expansion of RISC-V Ecosystem: By utilizing the X-HEEP framework and integrating Coprosit into a RISC-V system, the project demonstrates how specialized, power-optimized custom instructions and accelerators can be rapidly deployed and validated within the RISC-V ISA, furthering its appeal for application-specific processing.
• Future Wearable Design: The significant energy savings (up to 54%) directly translates to longer battery life or the ability to utilize smaller, lighter batteries, which is crucial for comfort and continuous operation in next-generation biomedical wearables.
• Modular Accelerator Design: The introduction of the PHEE architecture offers a blueprint for how future energy-efficient computing platforms can integrate domain-specific accelerators, moving away from generalized floating-point units to maximize efficiency for specific workloads.