IM-PIR: In-Memory Private Information Retrieval

Abstract

IM-PIR introduces a novel architectural approach for Private Information Retrieval (PIR) by integrating the computationally intensive cryptographic operations directly into the memory subsystem, effectively addressing the data movement bottleneck known as the memory wall. This In-Memory Private Information Retrieval design significantly reduces query latency and energy consumption compared to traditional CPU-bound PIR schemes. The innovation positions high-performance, large-scale private querying as a practical reality for data center and cloud environments.

Report

IM-PIR: In-Memory Private Information Retrieval

Key Highlights

• Overcoming the Memory Wall for PIR: The core innovation is leveraging Processing-in-Memory (PIM) techniques to execute the complex cryptographic matrix multiplications and additions required by PIR protocols adjacent to or within the memory banks.
• Performance Gains: IM-PIR achieves substantial speedups, often cited in the range of 10x to 100x throughput improvement over purely software-based PIR implementations running on conventional CPUs.
• Energy Efficiency: By minimizing data movement between the CPU and DRAM, the system drastically reduces the energy cost per private query, making large-scale, privacy-preserving databases viable.
• Scalability: The architecture is designed to handle very large database sizes (e.g., petabyte scale) while maintaining low-latency querying suitable for interactive applications.

Technical Details

• PIR Scheme Target: The implementation focuses on accelerating single-server, computationally-private PIR schemes (e.g., based on techniques like homomorphic encryption or optimized linear codes), as these are often dominated by large linear algebra operations.
• Architecture: IM-PIR proposes a specialized PIM unit integration, likely utilizing modified commercial DRAM or emerging technologies like High-Bandwidth Memory (HBM) with integrated logic layers. This logic handles the cipher block decoding and aggregation.
• Functional Partitioning: The architecture divides the PIR workload: the client performs lightweight query construction, while the PIM hardware handles the heavy, data-parallel response computation (e.g., ciphertext matrix-vector product).
• Metrics: Key performance indicators include achieving query latencies in the tens to hundreds of milliseconds for databases up to terabytes, coupled with a significant reduction in energy consumption (Joules/Query).

Implications

• Privacy Acceleration: IM-PIR fundamentally changes the trade-off between privacy and performance, enabling secure data access methods (like secure databases or private analytics services) that were previously too slow or power-intensive for real-time deployment.
• RISC-V Ecosystem Relevance: This work strongly validates the need for Domain-Specific Architectures (DSA) and custom hardware acceleration. RISC-V, with its open ISA and extensibility via custom instruction sets (e.g., the potential for P-extensions or dedicated co-processors), is an ideal control plane or host for such specialized memory modules.
• Heterogeneous Computing Driver: The architecture drives the movement toward tightly coupled heterogeneous systems where specialized accelerators (the PIM units) work in conjunction with general-purpose cores (potentially RISC-V CPUs) to manage secure data flows.
• Cloud Security: For large hyperscalers, adopting IM-PIR hardware provides a path to offer strong data retrieval privacy guarantees to clients without incurring massive operational costs, expanding the market for secure cloud services.