HW/SW Co-Design to Retarget the Compiler For RISC-V Custom Instructions (Tampere Univ.) - Semiconductor Engineering

Abstract

The research by Tampere University introduces an HW/SW co-design methodology aimed at efficiently integrating custom instruction set extensions (ISEs) into RISC-V cores. This approach specifically focuses on solving the typically time-consuming challenge of retargeting the compiler toolchain to recognize and optimally utilize these new hardware instructions. By streamlining the development flow, the innovation accelerates the design cycle for domain-specific RISC-V processors and accelerators.

Report

Structured Report: HW/SW Co-Design for RISC-V Custom Instructions

Key Highlights

• Toolchain Bottleneck Addressed: The primary innovation targets the complexity and time required to update compiler backends (like LLVM or GCC) every time a new set of custom instructions is added to a RISC-V core.
• Systematic Methodology: Tampere University proposes a structured HW/SW co-design flow to automate or semi-automate the creation of compiler description files based on the defined hardware extensions.
• Accelerated Customization: The approach enables faster iteration cycles for designers implementing domain-specific accelerators, leveraging the intrinsic flexibility of the RISC-V architecture.
• Focus on Efficiency: The methodology aims to ensure that the custom instructions are not only usable but are optimally selected and scheduled by the compiler for maximum performance gains.

Technical Details

• Unified Specification: The core technical detail likely involves using a unified description language (e.g., a high-level tool or DSL) to define the custom instruction semantics, register operations, and pipeline behavior.
• Dual Generation Path: This unified description is used to generate two essential outputs: the Register Transfer Level (RTL) code for the custom hardware unit and the compiler definition files (e.g., TableGen definitions for LLVM) necessary for instruction recognition, lowering, and scheduling.
• Compiler Retargeting: The process ensures the efficient mapping of high-level language constructs (like C/C++ intrinsic functions) directly to the new custom instructions, bypassing complex instruction emulation or library functions.
• Co-Design Loop: The methodology emphasizes continuous feedback between the hardware implementation specifics and the compiler’s optimization passes, optimizing factors like latency and resource usage.

Implications

• Democratization of Specialization: This type of automated co-design tool lowers the technical barrier for smaller teams and startups to create highly competitive, specialized RISC-V architectures without requiring deep expertise in compiler internals.
• Enhanced RISC-V Flexibility: It solidifies RISC-V's value proposition in specialized domains (e.g., AI/ML acceleration, signal processing, security) where custom instructions are essential for differentiating performance.
• Improved Time-to-Market: By reducing the often manual and error-prone process of toolchain integration, designers can prototype, test, and deploy customized hardware much faster, shortening the overall development cycle.
• Ecosystem Growth: Robust methodologies like this encourage wider adoption of RISC-V by providing necessary infrastructure to manage the complexity inherent in instruction set extensions.