Honest to a Fault: Root-Causing Fault Attacks with Pre-Silicon RISC Pipeline Characterization

Abstract

This paper presents a comprehensive methodology for conducting and root-causing controlled fault injection attacks at the pre-silicon level, tracing fault propagation from the physical layer to the system software. The study applies clock glitch attacks to RISC-V pipelines used in embedded AI/ML applications, demonstrating how hardware faults can induce critical misclassification errors. This analysis led to the discovery of a novel vulnerability exploitable through controlled clock glitch parameters specifically targeting the RISC-V decode stage.

Report

Key Highlights

• Pre-Silicon Fault Root-Causing: Introduction of a comprehensive methodology for diagnosing and understanding fault injection attacks entirely at the pre-silicon level.
• Cross-Layer Vulnerability Tracing: The research traces fault propagation across multiple layers of abstraction, including the physical implementation, microarchitecture, instruction set architecture (ISA), and system software.
• Target Application: Clock glitch attacks are demonstrated on AI/ML applications, proving that physical faults can cause critical misclassification errors.
• Novel Vulnerability Discovery: The study successfully characterized and diagnosed a previously unknown vulnerability using controlled clock glitch parameters.

Technical Details

• Target Architecture: The analysis focuses on characterizing and diagnosing fault impacts within the RISC-V instruction set and pipeline stages.
• Attack Vector: Controlled clock glitch attacks were utilized as the primary fault injection mechanism.
• Specific Discovery Location: The discovered novel vulnerability was specifically isolated to the RISC-V decode stage.
• Scope of Propagation: The methodology successfully traces the fault propagation path from the circuit level up to the high-level AI/ML application software behavior.

Implications

• Enhanced Hardware Security Design: By enabling pre-silicon fault characterization, designers can detect and mitigate hardware vulnerabilities much earlier in the development cycle, significantly reducing security risks and costs associated with post-silicon patching.
• RISC-V Ecosystem Security: The findings directly inform the security of RISC-V implementations, highlighting critical stages (like the decode stage) that require enhanced defensive measures against physical attacks.
• Embedded AI/ML System Integrity: The demonstration that clock glitches can cause critical misclassification emphasizes the necessity of robust physical security for embedded AI systems used in safety-critical applications.
• Holistic Security Approach: This work validates a methodology that links low-level physical phenomena (circuit glitches) directly to high-level software failure modes, supporting a more integrated approach to cyber infrastructure security.