HERO: Heterogeneous Embedded Research Platform for Exploring RISC-V Manycore Accelerators on FPGA

Abstract

HERO is an FPGA-based heterogeneous embedded research platform designed to combine an industry-standard host processor with an open, scalable programmable manycore accelerator (PMCA). The platform integrates a hard ARM Cortex-A multicore host with a PMCA built from clusters of soft RISC-V cores implemented on the FPGA fabric. HERO provides a complete software stack, including OpenMP support and a Linux driver, facilitating rapid hardware/software exploration and accurate run-time analysis via tracing.

Report

Key Highlights

• Platform Name: HERO (Heterogeneous Embedded Research Platform).
• Objective: To provide a research environment uniting an industry-standard host processor with an open research architecture for manycore accelerators.
• Architecture: Heterogeneous System on Chip (HESoC) combining a hard host processor and a soft manycore accelerator on an FPGA.
• Host: Hard ARM Cortex-A multicore processor.
• Accelerator Core: Clusters of soft RISC-V cores, forming a Programmable Manycore Accelerator (PMCA).
• Functionality: Supports fully automated hardware and software builds, testing, and accurate run-time analysis via event tracing.

Technical Details

• Host Component: Utilizes a hard ARM Cortex-A multicore host processor, ensuring compatibility with standard industry practices.
• Accelerator Component: The PMCA uses RISC-V cores implemented as soft cores on the FPGA fabric.
• PMCA Features: The accelerator architecture is described as silicon-proven, highly scalable, configurable, and fully modifiable by researchers.
• Software Ecosystem: Includes a complete heterogeneous cross-compilation toolchain.
• Programming Model: Offers explicit support for OpenMP accelerator programming.
• Operating System Integration: Features a Linux driver for communication and management between the host and the PMCA, alongside necessary runtime libraries for both components.

Implications

• Enabling Research: HERO addresses a critical gap by providing a prototyping platform that allows academic research to keep pace with industry advancements in HESoCs, particularly by enabling deep modification of the accelerator architecture.
• RISC-V Ecosystem Growth: By integrating scalable RISC-V soft cores into a high-performance heterogeneous system alongside a standard ARM host, HERO validates the viability and performance of open ISA accelerators for embedded computing.
• Accelerated Development Cycle: The inclusion of automated build systems, comprehensive software tooling (like OpenMP support), and precise run-time tracing significantly lowers the barrier to entry and speeds up the validation process for novel hardware and software co-design methodologies.
• Open Architecture Promotion: The platform serves as a powerful demonstration of how open-source, configurable RISC-V designs can be successfully deployed and studied in complex, real-world heterogeneous computing scenarios.