GSIM: Accelerating RTL Simulation for Large-Scale Designs

Abstract

This paper introduces GSIM, a novel RTL simulator designed to overcome the severe simulation bottleneck encountered in modern, large-scale hardware designs. The authors explore and optimize four major sources of computation overhead through new techniques implemented at the supernode, node, and bit levels. GSIM achieves impressive performance gains, demonstrating a 7.34x speedup over Verilator when booting Linux on the XiangShan RISC-V processor and a 19.94x speedup running CoreMark on Rocket.

Report

Key Highlights

• New Simulator: Introduction of GSIM, a novel Register Transfer Level (RTL) simulator targeting acceleration for large-scale designs.
• Bottleneck Mitigation: GSIM specifically addresses the slowness of software RTL simulation, which is identified as the primary bottleneck in modern hardware design flow.
• High Performance Gains: Achieves a 7.34x speedup compared to Verilator when performing complex tasks (booting Linux) on the XiangShan processor.
• Maximum Speedup: Demonstrates a 19.94x speedup over Verilator when executing the CoreMark benchmark on the Rocket processor.
• Validated on Complex Cores: Successfully simulates the state-of-the-art open-source RISC-V processor, XiangShan, confirming its viability for complex architectures.

Technical Details

• Optimization Focus: The research identifies four distinct sources of computation overhead inherent in traditional software RTL simulation.
• Multi-Level Optimization: GSIM employs specific optimization techniques applied across three different abstraction layers: the supernode level, the node level, and the bit level.
• Implementation: The techniques are integrated into the implementation of the novel RTL simulator, GSIM.
• Comparative Benchmark: Performance results utilize Verilator as the primary comparison baseline.

Implications

• Accelerated RISC-V Development: By dramatically accelerating simulation speeds (up to nearly 20x), GSIM removes a critical bottleneck in the design space exploration, verification, and debugging phases for large RISC-V cores like XiangShan and Rocket.
• Enhanced Verification Capabilities: Faster simulation allows hardware teams to run more extensive and complex test suites (like booting an operating system such as Linux) in practical time frames, leading to higher quality and more reliable designs.
• Cost Efficiency: While software simulation is valued for its flexibility and low setup cost, GSIM mitigates its historical disadvantage (speed), making software-based verification a more viable and efficient option for industrial-scale projects.
• Advancement of Open Source Hardware: The successful simulation of state-of-the-art open-source designs (XiangShan) confirms that GSIM can serve as a powerful tool for the continued development and iteration of complex open-source RISC-V architectures.