Functional ISS-Driven Verification of Superscalar RISC-V Processors

Abstract

This paper introduces SupeRFIVe, a novel methodology designed for the time-efficient and comprehensive functional verification of complex superscalar processors. SupeRFIVe leverages an Instruction Set Simulator (ISS) as a golden reference, interfacing with the Design Under Test (DUT) testbench through socket communication for accurate validation. The effectiveness of the method is demonstrated by applying it to verify the functional correctness of a RISC-V dual-issue superscalar CPU using the Spike simulator and open-source benchmark applications.

Report

Key Highlights

• SupeRFIVe Methodology: Introduction of a novel, simulation-based methodology for the functional verification of superscalar processors.
• ISS-Driven Validation: The method utilizes an Instruction Set Simulator (ISS) (specifically Spike) as a golden reference model to comprehensively validate the correctness of the Design Under Test (DUT).
• Socket Communication: Validation is achieved by interfacing the DUT testbench with the ISS via socket communication, facilitating efficient and continuous state comparison during simulation.
• Target Application: Successfully applied to verify a complex RISC-V dual-issue superscalar CPU, addressing a key challenge in modern hardware design.

Technical Details

• Methodology Name: SupeRFIVe (Superscalar Functional RISC-V Verification).
• Design Under Test (DUT): A RISC-V dual-issue superscalar CPU architecture.
• Reference Tool: Leverages Spike, the state-of-the-art RISC-V instruction set simulator, to provide expected architectural state updates.
• Verification Mechanism: Functional verification based on a co-simulation approach, where the DUT's behavior is continuously checked against the golden reference model (Spike) while executing benchmark applications.
• Interfacing: The testbench and the ISS communicate through socket mechanisms.

Implications

• Addressing Complexity: Provides a critical verification solution necessary for mitigating risks associated with highly complex, out-of-order or superscalar RISC-V implementations, which are significantly harder to verify than single-issue cores.
• Ecosystem Standardization: By utilizing widely adopted tools like Spike, the methodology promotes standard, reliable, and reusable verification practices within the growing open-source RISC-V ecosystem.
• Accelerated Design Cycle: Offers a time-efficient approach to achieving comprehensive verification coverage, potentially speeding up the design and tape-out readiness of high-performance RISC-V CPU cores.