FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on Tomasulo's Algorithm
Originally published on ArXiv - Hardware Architecture
Computer Science > Hardware Architecture
arXiv:2506.07665v1 (cs)
[Submitted on 9 Jun 2025]
Title:FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on Tomasulo's Algorithm
Authors:Roberto Giorgi
View a PDF of the paper titled FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on Tomasulo's Algorithm, by Roberto Giorgi
Abstract:FREESS is a free, interactive simulator that illustrates instruction-level parallelism in a RISC-V-inspired superscalar processor. Based on an extended version of Tomasulo's algorithm, FREESS is intended as a hands-on educational tool for Advanced Computer Architecture courses. It enables students to explore dynamic, out-of-order instruction execution, emphasizing how instructions are issued as soon as their operands become available.
The simulator models key microarchitectural components, including the Instruction Window (IW), Reorder Buffer (ROB), Register Map (RM), Free Pool (FP), and Load/Store Queues. FREESS allows users to dynamically configure runtime parameters, such as the superscalar issue width, functional unit types and latencies, and the sizes of architectural buffers and queues.
To simplify learning, the simulator uses a minimal instruction set inspired by RISC-V (ADD, ADDI, BEQ, BNE, LW, MUL, SW), which is sufficient to demonstrate key pipeline stages: fetch, register renaming, out-of-order dispatch, execution, completion, commit, speculative branching, and memory access. FREESS includes three step-by-step, illustrated examples that visually demonstrate how multiple instructions can be issued and executed in parallel within a single cycle. Being open source, FREESS encourages students and educators to experiment freely by writing and analyzing their own instruction-level programs and superscalar architectures.
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Subjects:
Hardware Architecture (cs.AR)
ACM classes:
C.1.2; C.1.3; K.3.2
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arXiv:2506.07665 [cs.AR]
(or arXiv:2506.07665v1 [cs.AR] for this version)
https://doi.org/10.48550/arXiv.2506.07665
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arXiv-issued DOI via DataCite
Submission history
From: Roberto Giorgi [view email]
[v1] Mon, 9 Jun 2025 11:38:33 UTC (6,958 KB)
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AI Analysis
Key Highlights
- Educational Focus: FREESS is explicitly designed as a hands-on tool for Advanced Computer Architecture courses.
- Core Algorithm: Based on an extended version of Tomasulo's algorithm to illustrate dynamic, out-of-order execution.
- Architecture Inspiration: Models a superscalar processor inspired by the RISC-V Instruction Set Architecture (ISA).
- Accessibility: The simulator is free, interactive, open source, and includes three illustrated step-by-step examples.
- Configurability: Allows users to dynamically adjust critical runtime parameters, such as issue width, functional unit latencies, and buffer sizes.
Technical Details
- Execution Paradigm: Demonstrates instruction-level parallelism and out-of-order dispatch, emphasizing issuing instructions as soon as operands are available.
- Modeled Microarchitectural Components: The simulator includes detailed models of the Instruction Window (IW), Reorder Buffer (ROB), Register Map (RM), Free Pool (FP), and Load/Store Queues.
- Pipeline Stages Covered: The simulation visually tracks and demonstrates key pipeline stages: fetch, register renaming, out-of-order dispatch, execution, completion, commit, speculative branching, and memory access.
- Instruction Set: Utilizes a minimal, RISC-V-inspired instruction set sufficient for demonstration: ADD, ADDI, BEQ, BNE, LW (Load Word), MUL, and SW (Store Word).
- Dynamic Configuration: Users can customize settings such as the superscalar issue width, specific functional unit types and their latencies, and the capacity of architectural buffers and queues.
Implications
- Improved Computer Architecture Pedagogy: FREESS addresses a common difficulty in computer science education by providing a tangible, visual, and interactive model for highly complex, dynamic concepts like Tomasulo's algorithm and pipeline hazards, which are difficult to grasp purely theoretically.
- Support for RISC-V Education: By using a RISC-V-inspired ISA, the simulator helps bridge the gap between theoretical architecture concepts and modern, relevant processor design, aiding in the training of future engineers familiar with the growing RISC-V ecosystem.
- Open Source Contribution: The open-source nature of FREESS encourages broader experimentation, adaptation, and contribution from educators and students globally, fostering a collaborative learning environment for advanced topics.
