FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on Tomasulo's Algorithm

Abstract

FREESS is a new free, interactive educational simulator designed to teach instruction-level parallelism in advanced computer architecture courses. It models a RISC-V-inspired superscalar processor utilizing an extended Tomasulo's algorithm for dynamic, out-of-order instruction execution. The tool allows dynamic configuration of microarchitectural parameters and includes visual, step-by-step examples covering all key pipeline stages, making complex concepts accessible.

Report

Key Highlights

• Educational Focus: FREESS is explicitly designed as a hands-on tool for Advanced Computer Architecture courses.
• Core Algorithm: Based on an extended version of Tomasulo's algorithm to illustrate dynamic, out-of-order execution.
• Architecture Inspiration: Models a superscalar processor inspired by the RISC-V Instruction Set Architecture (ISA).
• Accessibility: The simulator is free, interactive, open source, and includes three illustrated step-by-step examples.
• Configurability: Allows users to dynamically adjust critical runtime parameters, such as issue width, functional unit latencies, and buffer sizes.

Technical Details

• Execution Paradigm: Demonstrates instruction-level parallelism and out-of-order dispatch, emphasizing issuing instructions as soon as operands are available.
• Modeled Microarchitectural Components: The simulator includes detailed models of the Instruction Window (IW), Reorder Buffer (ROB), Register Map (RM), Free Pool (FP), and Load/Store Queues.
• Pipeline Stages Covered: The simulation visually tracks and demonstrates key pipeline stages: fetch, register renaming, out-of-order dispatch, execution, completion, commit, speculative branching, and memory access.
• Instruction Set: Utilizes a minimal, RISC-V-inspired instruction set sufficient for demonstration: ADD, ADDI, BEQ, BNE, LW (Load Word), MUL, and SW (Store Word).
• Dynamic Configuration: Users can customize settings such as the superscalar issue width, specific functional unit types and their latencies, and the capacity of architectural buffers and queues.

Implications

• Improved Computer Architecture Pedagogy: FREESS addresses a common difficulty in computer science education by providing a tangible, visual, and interactive model for highly complex, dynamic concepts like Tomasulo's algorithm and pipeline hazards, which are difficult to grasp purely theoretically.
• Support for RISC-V Education: By using a RISC-V-inspired ISA, the simulator helps bridge the gap between theoretical architecture concepts and modern, relevant processor design, aiding in the training of future engineers familiar with the growing RISC-V ecosystem.
• Open Source Contribution: The open-source nature of FREESS encourages broader experimentation, adaptation, and contribution from educators and students globally, fostering a collaborative learning environment for advanced topics.